TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-42 V2.0, 2007-07
SSC, V2.1
The Transmit FIFO Control Register TXFCON (only available in SSC0) contains control
bits and bit fields that determine the operating mode of the RXFIFO.
SSC0_TXFCON
SSC0 Transmit FIFO Control Register (34
H
) Reset Value: 0000 0100
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0TXFITL 0
TX
TM
EN
TXF
FLU
TXF
EN
r rw r rwwrw
Field Bits Type Description
TXFEN 0rwTXFIFO Enable
0
B
TXFIFO is disabled
1
B
TXFIFO is enabled
Note: Resetting TXFEN automatically flushes the
TXFIFO.
TXFFLU 1wTXFIFO Flush
0
B
No operation
1
B
TXFIFO is flushed
Note: Setting TXFFLU clears bit field TXFFL in
register FSTAT. TXFFLU is always read as 0.
TXTMEN 2rwTXFIFO Transparent Mode Enable
0
B
TXFIFO Transparent Mode is disabled
1
B
TXFIFO Transparent Mode is enabled
Note: This bit is “don’t care” if the TXFIFO is disabled
(TXFEN = 0).
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