TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-41 V2.0, 2007-07
SSC, V2.1
RXFITL [11:8] rw RXFIFO Interrupt Trigger Level
1)
Determines the RXFIFO interrupt trigger level. A
receive interrupt request (RIR) is always generated
after the reception of a byte when the filling level of the
RXFIFO is equal to or greater than RXFITL.
0000
B
Reserved. Do not use this combination
0001
B
Interrupt trigger level is set to 1
0010
B
Interrupt trigger level is set to 2
…
B
…
0111
B
Interrupt trigger level is set to 7
1000
B
Interrupt trigger level is set to 8
Other combinations of RXFITL are reserved and
should not be used.
Note: In Transparent Mode this bit field is “don’t care”.
0 [7:3],
[31:12]
r Reserved
Read as 0; should be written with 0.
1) In the SSC0 module with the 8-stage RXFIFO, the most significant bit of RXFITL (= RXFCON.12) is always
read as 0 and should be written with 0.
Field Bits Type Description
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