TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-57 V2.0, 2007-07
SSC, V2.1
Pad Driver Mode Registers
The Port 2 and Port 6 Pad Driver Mode Registers contain bit fields that determine the
output driver strength, and the slew rate of SSC output lines.
P2_PDR
Port 2 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
H
31 22 20 18 16 0
0
PD
SLS1
0
PD
SLS0
0 PD1 0
rrwrrw r rw r
Field Bits Type Description
PDSLS0 [18:16] rw Pad Driver Mode for P2.[3:2]/SLSO[3:2]
1)
1) Coding of bit field see Table 20-6. Shaded bits and bit fields are “don’t care” for SSC I/O port control.
PDSLS1 [22:20] rw Pad Driver Mode for P2.[7:4]/SLSO[7:4]
1)
P6_PDR
Port 6 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
HH
31 22 20 18 16 0
0
PD
CANCD
0
PD
CANAB
0
PD
SSC1
0 0 0
r rw r rw rrwr rw r
Field Bits Type Description
PDSSC1 [22:20] rw Pad Driver Mode for P6.4/MTSR1, P6.5/MRST1,
and P6.6/SCLK1
1)
1) Coding of bit field see Table 20-6. Shaded bits and bit fields are “don’t care” for SSC I/O port control.
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