Infineon Technologies TC1796 - Page 1260

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-43 V2.0, 2007-07
MSC, V2.0
Note: The rw bits in the DSC register are buffered in a shadow buffer at the start of a
corresponding frame transmission.
DSDIS 15 rh Downstream Disable
This bit indicates the state of the downstream channel
operation.
0
B
The downstream channel is enabled. A frame
transmission can take place (Triggered Mode) or
takes place (Data Repetition Mode).
1
B
Downstream Counter becomes disabled. No new
frame transmission is started. A running frame
transmission is always completed.
NBC [21:16] rw Number of Bits Shifted at Command Frames
This bit field determines how many bits of the SRL/SRH
shift registers are shifted out during transmission of a
command frame.
000000
B
No bit shifted
000001
B
SRL[0] shifted
000010
B
SRL[1:0] shifted
000011
B
SRL[2:0] shifted
…
B
…
010000
B
SRL[15:0] shifted
010001
B
SRL[15:0] and SRH[0] shifted
010010
B
SRL[15:0] and SRH[1:0] shifted
…
B
…
011111
B
SRL[15:0] and SRH[14:0] shifted
100000
B
SRL[15:0] and SRH[15:0] shifted
Other bit combinations are reserved; do not use these bit
combinations
PPD [28:24] rw Passive Phase Length at Data Frames
This bit field determines the length of the passive phase
of a data frame.
00000
B
Passive phase length is 2 × t
FCL
00001
B
Passive phase length is 2 × t
FCL
00010
B
Passive phase length is 2 × t
FCL
00011
B
Passive phase length is 3 × t
FCL
…
B
…
11111
B
Passive phase length is 31 × t
FCL
0 [23:22],
[31:29]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description