Infineon Technologies TC1796 - Page 1259

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-42 V2.0, 2007-07
MSC, V2.0
NDBL [7:3] rw Number of SRL Bits Shifted at Data Frames
NDBL determines the number of shift register low part
(SRL) bits that are shifted out on SO during a data frame.
00000
B
No SRL bit shifted
00001
B
SRL[0] shifted
00010
B
SRL[1:0] shifted
…
B
…
01111
B
SRL[14:0] shifted
10000
B
SRL[15:0] shifted
Other bit combinations are reserved; do not use these bit
combinations.
NDBH [12:8] rw Number of SRH Bits Shifted at Data Frames
NDBH determines the number of shift register high part
(SRH) bits that are shifted out on SO during a data
frame.
00000
B
No SRH bit shifted; no selection bit is
generated, the SRH active phase is
completely skipped.
00001
B
SRH[0] shifted
00010
B
SRH[1:0] shifted
…
B
…
01111
B
SRH[14:0] shifted
10000
B
SRH[15:0] shifted
Other bit combinations are reserved; do not use these bit
combinations.
ENSELL 13 rw Enable SRL Active Phase Selection Bit
This bit determines whether a low-level selection bit is
inserted at the beginning of a data frame’s SRL active
phase.
0
B
No selection bit inserted.
1
B
Low-level selection bit inserted.
ENSELH 14 rw Enable SRH Active Phase Selection Bit
This bit determines whether a low-level selection bit is
inserted at the beginning of a data frame’s SRH active
phase.
0
B
No selection bit inserted.
1
B
Low-level selection bit inserted.
Field Bits Type Description