Infineon Technologies TC1796 - Page 1265

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-48 V2.0, 2007-07
MSC, V2.0
The Emergency Stop Register ESR determines which bits of SRL and SRH are enabled
for emergency operation.
ESR
Emergency Stop Register (2C
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENH
15
ENH
14
ENH
13
ENH
12
ENH
11
ENH
10
ENH
9
ENH
8
ENH
7
ENH
6
ENH
5
ENH
4
ENH
3
ENH
2
ENH
1
ENH
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
ENL
15
ENL
14
ENL
13
ENL
12
ENL
11
ENL
10
ENL
9
ENL
8
ENL
7
ENL
6
ENL
5
ENL
4
ENL
3
ENL
2
ENL
1
ENL
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Field Bits Type Description
ENLx
(x = 0-15)
xrwEmergency Stop Enable for Bit x in SRL
This bit enables the emergency stop feature
selectively for each SRL bit. If the emergency stop
condition is met and enabled (ENLx = 1), the SRL[x]
bit is of the data register DD.DDL[x] is used for the
shift register load operation.
0
B
Emergency stop feature for bit SRL[x] is
disabled.
1
B
The emergency stop feature for bit SRL[x] is
enabled.
ENHx
(x = 0-15)
x+16 rw Emergency Stop Enable for Bit x in SRH
This bit enables the emergency stop feature
selectively for each SRH bit. If the emergency stop
condition is met and enabled (ENHx = 1), the SRH[x]
bit of the data register DD.DDH[x] is used for the shift
register load operation.
0
B
Emergency stop feature for bit SRH[x] is
disabled.
1
B
The emergency stop feature for bit SRH[x] is
enabled.