Infineon Technologies TC1796 - Page 1274

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-57 V2.0, 2007-07
MSC, V2.0
CLKCTRL 8rwClock Control
This bit determines the activation of clock output
FCL.
0
B
FCL is activated only during the active phases
of data or command frames (not during
passive time frames).
1
B
FCL is always active whether or not a
downstream frame is currently transmitted.
CSL [10:9] rw Chip Enable Selection for ENL
This bit field selects the chip enable output ENx that
becomes active during the SRL active phase
(ENL = 1) of a data frame. The active level of ENx is
defined by bit CSLP.
00
B
EN0 line is selected for ENL.
01
B
EN1 line is selected for ENL.
10
B
EN2 line is selected for ENL.
11
B
EN3 line is selected for ENL.
CSH [12:11] rw Chip Enable Selection for ENH
This bit field selects the chip enable output ENx that
becomes active during the SRL active phase
(ENH = 1) of a data frame. The active level of ENx is
defined by bit CSLP.
00
B
EN0 line is selected for ENH.
01
B
EN1 line is selected for ENH.
10
B
EN2 line is selected for ENH.
11
B
EN3 line is selected for ENH.
CSC [14:13] rw Chip Enable Selection for ENC
This bit field selects the chip enable output ENx that
becomes active during the active phase (ENC = 1) of
a command frame. The active level of ENx is defined
by bit CSLP.
00
B
EN0 line is selected for ENC.
01
B
EN1 line is selected for ENC.
10
B
EN2 line is selected for ENC.
11
B
EN3 line is selected for ENC.
Field Bits Type Description