Infineon Technologies TC1796 - Page 1283

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-66 V2.0, 2007-07
MSC, V2.0
The following two formulas define the frequency of f
MSC0
or f
MSC1
(x = 1, 0):
(21.3)
(21.4)
Downstream Channel Baud Rate
As the clock signal FCL of the synchronous downstream channel is always half the
frequency of f
MSCx
, the resulting downstream channel baud rate is defined by:
(21.5)
(21.6)
Upstream Channel Baud Rate
The baud rate of the asynchronous upstream channel is derived from the module clock
f
MSCx
by a programmable clock divider selected by bit field MSCx_USR.URR (see also
Equation (21.2) on Page 21-25). The divide factor DF can be at minimum 4 and at
maximum 256.
(21.7)
(21.8)
Equation (21.3), Equation (21.5), and Equation (21.7) are valid for normal divider
mode (MSCx.FDR.DM = 01
B
). Equation (21.4), Equation (21.6), and Equation (21.8)
are valid for fractional divider mode (MSCx.FDR.DM = 10
B
).
f
MSCx
f
SYS
1
n
---
× with n = 1024 - MSCx.FDR.STEP =
f
MSCx
f
SYS
n
1024
-------------
× with n = 0-1023 =
Baud rate
MSCx
f
SYS
1
2 1024 - MSCx.FDR.STEP()×
--------------------------------------------------------------------------------
×=
Baud rate
MSCx
f
SYS
MSCx.FDR.STEP
2 1024×
-----------------------------------------------
×=
Baud rate
MSCx
f
SYS
1
DF 1024 - MSCx.FDR.STEP()×
-------------------------------------------------------------------------------------
×=
Baud rate
MSCx
f
SYS
MSCx.FDR.STEP
DF 1024×
-----------------------------------------------
×=