TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-131 V2.0, 2007-07
MultiCAN, V2.0
Note: The interrupt settings of a valid interrupt control entry overrule the previously
stored interrupt settings for the next time mark. As a result, the use of more than
one valid interrupt control entry between two time mark entries should be avoided.
Arbitration Entry
The arbitration entry is defined as follows:
0 [7:6],
[15:14],
[27:24]
r Reserved; read as 0; should be written with 0. Bits
are “don’t care” for scheduler operation when
EC = 0011
B
.
ARBE
Arbitration Entry
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0011 0 ARBM 0
rw rw rw rw r rw r
1514131211109876543210
0 MCYCLE 0 CYCLE
rrw rrw
Field Bits Type Description
CYCLE [5:0] rw Basic Cycle Number
This bit field determines the number of the basic
cycle during which this arbitration entry is valid. The
value of CYCLE is compared (bit-wise) with the
current value of bit field CYCTMR.BCC. The result
is then masked with the value given by the bit field
MCYCLE in order to determine the repetition rate for
this scheduler entry inside the matrix cycle.
This bit field is equivalent to the corresponding part
of the MOAMRn.AM bit field (see Page 22-108).
Field Bits Type Description
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