Infineon Technologies TC1796 - Page 1477

TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-182 V2.0, 2007-07
MultiCAN, V2.0
The Time Trigger Interrupt Request Register TTIRR contains the time trigger status
information related to interrupt events. Note that all bits in TTIRR can be cleared by
software by writing 0 to it. Writing a 1 to the bits has no effect.
TTIRR
Time Trigger Interrupt Request Register
(2D0
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
TUR
ERR
CFG
ERR
rrwhrwh
1514131211109876543210
SER
R2
SER
R1
DISC WFE EOS
SYN
CSC
MSR
C
ERR
SC
AWD
ERR
I
WTE
WTE
TT
OF
TT
UF
TEN
WER
NBC NMC
rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh
Field Bits Type Description
NMC 0rwhNew Matrix Cycle
This bit indicates that a new matrix cycle has started.
It is set when a reference message with the cycle
count = 0 has been transferred correctly.
0
B
A new matrix cycle has not yet been detected.
1
B
A new matrix cycle has been detected.
NBC 1rwhNew Basic Cycle
This bit indicates that a new basic cycle has started.
0
B
A new basic cycle has not yet been detected.
10
B
A new basic cycle has been detected.
TENWER 2rwhTransmit Enable Window Error
This bit indicates that the specified time elapsed after
the transmit trigger without starting the transmission
of a message.
0
B
The triggered messages have been sent out
before the transmit enable window elapsed.
1
B
A triggered message was not started before
the transmit enable window elapsed.