TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-198 V2.0, 2007-07
MultiCAN, V2.0
Note: This register is reset at the start of a new instruction collection phase.
TMEV 20 rh Time Mark Entry Valid
This bit indicates that a valid time mark entry has
been found during the instruction collection for this
time window. It is automatically cleared when a time
mark is reached.
0
B
No valid TME has been found
1
B
A valid TME has been found
RMEV 21 rh Reference Mark Entry Valid
This bit indicates that a valid reference mark entry
has been found during the instruction collection for
this time window. It is automatically cleared when a
time mark is reached.
0
B
No valid RME has been found
1
B
A valid RME has been found
BCEV 22 rh Basic Cycle End Entry Valid
This bit indicates that a valid basic cycle end entry
has been found during the instruction collection for
this time window. It is automatically cleared when a
time mark is reached.
0
B
No valid BCE has been found
1
B
A valid BCE has been found
0 [31:23] r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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