Infineon Technologies TC1796 - Page 1593

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-84 V2.0, 2007-07
MLI, V2.0
The Output Input Control Register OICR determines the functionality of the MLI
transmitter and MLI receiver I/O control logic.
The bits in this register are automatically overwritten after a reset with a value given in
the implementation chapter (see Page 23-127). Furthermore, the connection table of the
MLI module signals is given there.
OICR
Output Input Control Register (B4
H
) Reset Value: 1000 8000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDP RDS RCE RCP RCS RVP RVS
RRP
D
RRP
C
RRP
B
RRP
A
RRS
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVE TDP TCP TCE TRE TRP TRS
TVP
D
TVP
C
TVP
B
TVP
A
TVE
D
TVE
C
TVE
B
TVE
A
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Field Bits Type Description
TVEA,
TVEB,
TVEC,
TVED
0,
1,
2,
3
rw Transmitter Valid Enable
These bits enable the module kernel output signals
TVALIDx (x = A, B, C, D) to be driven by MLI transmitter
output signal TVALID.
0
B
TVALIDx is disabled and remains at passive level
(as selected by TVPx).
1
B
Transmitter output signal TVALIDx is enabled and
driven by TVALID.
TVPA,
TVPB,
TVPC,
TVPD
4,
5,
6,
7
rw Transmitter Valid Polarity
These bits determine the polarity of the module kernel
transmitter output signals TVALIDx (x = A, B, C, D).
0
B
Non-inverted polarity for TVALIDx selected:
TVALIDx is passive when driving a 0. TVALIDx is
active when driving a 1.
1
B
Inverted polarity for TVALIDx selected:
TVALIDx is passive when driving a 1. TVALIDx is
active when driving a 0.