TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-85 V2.0, 2007-07
MLI, V2.0
TRS [9:8] rw Transmitter Ready Selection
This bit field determines the module kernel input signal
TREADYx (x = A, B, C, D) that is used as MLI
transmitter input signal TREADY.
00
B
TREADYA is selected.
01
B
TREADYB is selected.
10
B
TREADYC is selected.
11
B
TREADYD is selected.
TRP 10 rw Transmitter Ready Polarity
This bit determines the polarity of TREADYx.
0
B
Non-inverted polarity for TREADYx selected:
TREADYx is passive if 0. TREADYx is active if 1.
1
B
Inverted polarity for TREADYx selected:
TREADYx is passive if 1. TREADYx if 0.
TRE 11 rw Transmitter Ready Enable
This bit enables the MLI transmitter input signal
TREADY.
0
B
TREADY signal is disabled (always at 0 level).
1
B
TREADY signal is enabled and driven by
TREADYx according to the settings of TRS and
TRP.
TCE 12 rw Transmitter Clock Enable
This bit enables the module kernel output signal TCLK.
0
B
TCLK is disabled and remains at passive level (as
selected by TCP).
1
B
TCLK is enabled and driven according to the
setting of TCP.
TCP 13 rw Transmitter Clock Polarity
This bit determines the polarity of the module kernel
output clock signal TCLK.
0
B
Non-inverted polarity for TCLK selected:
TCLK is driving a 0 when it is passive.
1
B
Inverted polarity for TCLK selected:
TCLK is driving a 1 when it is passive.
Field Bits Type Description
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