Infineon Technologies TC1796 - Page 1595

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-86 V2.0, 2007-07
MLI, V2.0
TDP 14 rw Transmitter Data Polarity
This bit determines the polarity of the module kernel
output clock signal TDATA.
0
B
TDATA is directly driven by MLI transmitter output
signal TDATA (non-inverted).
1
B
TDATA is directly driven by the inverted MLI
transmitter output signal TDATA.
RVE 15 rw Receiver Valid Enable
This bit enables the MLI receiver input signal RVALID.
0
B
RVALID signal is disabled (always at 0 level).
1
B
RVALID signal is enabled and driven by RVALIDx
according to the settings of RVS and RVP
(default after reset).
RRS [17:16] rw Receiver Ready Selector
This bit field determines the module kernel output signal
RREADYx (x = A, B, C, D) that is driven by the MLI
receiver output signal RREADY. The RREADYx output
signals that are not selected drives a passive level
according to the setting of RRPx.
00
B
RREADYA is selected.
01
B
RREADYB is selected.
10
B
RREADYC is selected.
11
B
RREADYD is selected.
RRPA,
RRPB,
RRPC,
RRPD
18,
19,
20,
21
rw Receiver Ready Polarity
These bits determine the polarity of the module kernel
receiver output signals RREADYx (x = A, B, C, D).
0
B
Non-inverted polarity for RREADYx selected:
RREADYx is passive if 0. RREADYx is active if 1.
1
B
Inverted polarity for RREADYx selected:
RREADYx is passive if 1. RREADYx is active if 0.
RVS [23:22] rw Receiver Valid Selector
This bit field determines the module kernel input signal
RVALIDx (x = A, B, C, D) that is used as MLI receiver
input signal RVALID.
00
B
RVALIDA is selected.
01
B
RVALIDB is selected.
10
B
RVALIDC is selected.
11
B
RVALIDD is selected.
Field Bits Type Description