TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-87 V2.0, 2007-07
MLI, V2.0
RVP 24 rw Receiver Valid Polarity
This bit determines the polarity of RVALIDx.
0
B
Non-inverted polarity for RVALIDx selected:
RVALIDx is passive if 0. RVALIDx is active if 1.
1
B
Inverted polarity for RVALIDx selected:
RVALIDx is passive if 1. RVALIDx is active if 0.
RCS [26:25] rw Receiver Clock Selector
This bit field determines the module kernel input signal
RCLKx (x = A, B, C, D) that is used as MLI receiver
input clock CLK.
00
B
RCLKA is selected.
01
B
RCLKB is selected.
10
B
RCLKC is selected.
11
B
RCLKD is selected.
RCP 27 rw Receiver Clock Polarity
This bit determines the polarity of RCLKx.
0
B
Non-inverted polarity for RCLKx selected:
RCLKx is at 0 level in passive state.
1
B
Inverted polarity for TCLK selected:
RCLKx is at 1 level in passive state.
RCE 28 rw Receiver Clock Enable
This bit enables the MLI receiver input clock RCLK.
0
B
RCLK signal is disabled (always at 0 level).
1
B
RCLK signal is enabled and driven by RCLKx
according to the settings of RCS and RCP.
RDS [30:29] rw Receiver Data Selector
This bit field determines the module kernel input signal
RDATAx (x = A, B, C, D) that is used as MLI receiver
data input line RDATA.
00
B
RDATAA is selected.
01
B
RDATAB is selected.
10
B
RDATAC is selected.
11
B
RDATAD is selected.
RDP 31 rw Receiver Data Polarity
This bit determines the polarity of RDATAx.
0
B
Non-inverted polarity for RDATAx selected:
RDATAx is passive if 0. RDATAx is active if 1.
1
B
Inverted polarity for RDATAx selected:
RDATAx is passive if 1. RDATAx is active if 0.
Field Bits Type Description
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