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Infineon Technologies TC1796 - Page 1602

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TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-93 V2.0, 2007-07
MLI, V2.0
The Transmitter Status Register TSTATR contains transmitter specific status
information.
TSTATR
Transmitter Status Register (14
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0 NAE PE APN RDC
rrhrhrhrh
Field Bits Type Description
RDC [4:0] rh Ready Delay Counter
This bit field counts TCLK periods after the end of a
frame transmission. When the TVALID signal goes to
low level, RDC is cleared to zero and starts counting up
the TCLK clock periods until a TREADY high level is
detected (see Page 23-22).
APN [6:5] rh Answer Pipe Number
This bit field is written by the MLI receiver with the Pipe
Number of a received Read Frame. APN is used by an
Answer Frame that is transmitted as response to the
Read Frame.
00
B
Pipe 0 is used in Answer Frame.
01
B
Pipe 1 is used in Answer Frame.
10
B
Pipe 2 is used in Answer Frame.
11
B
Pipe 3 is used in Answer Frame.
PE 7rhParity Error Flag
This bit is set if a transmitter parity error condition is
detected by the transmitter after a frame transmission.
PE is cleared by hardware when a frame has been
transmitted without a parity error (see Page 23-42). Bit
PE can be cleared by software via bit SCR.CTPE.

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