TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-92 V2.0, 2007-07
MLI, V2.0
MDP [13:10] rw Maximum Delay for Parity Error
This bit field determines a window for the transmitter in
number of TCLK clock periods where a TREADY low-
to-high signal transition signal is considered as
“correctly received” condition (see Page 23-22).
0000
B
Zero clock periods selected (not useful)
0001
B
1 clock period selected
…
B
…
1110
B
14 clock periods selected
1111
B
15 clock periods selected
NO 14 rw No Optimized Method
This bit field enables/disables the address prediction
for Read or Write Frames (see Page 23-45).
0
B
Optimized method (address prediction) enabled.
1
B
Optimized method (address prediction) disabled.
TP 15 rw Type of Parity
This bit will determines the type of parity used in frame
transmissions. For correct data transfers, TP = 0 has to
be programmed. The value TP = 1 can be selected to
force parity errors to analyze the propagation delay
(see Page 23-24).
0
B
Even parity selected; parity bit P is set when the
modulo-2 sum of frame header bits and data field
bits is 1.
1
B
Odd parity selected; parity bit P is set when the
modulo-2 sum of frame header bits and data field
bits is 0.
0 3,
[31:16]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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