Infineon Technologies TC1796 - Page 1604

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-95 V2.0, 2007-07
MLI, V2.0
The Transmitter Pipe x Status Registers TPxSTATR contain pipe-specific status
information related to address optimization and prediction, data width for transmit data,
and Remote Window size.
TPxSTATR (x = 0-3)
Transmitter Pipe x Status Register
(18
H
+4
H
*x) Reset Value: 0000 0000
H
31 17 16 15 6 5 4 3 0
0
O
P
AP DW BS
rrhrhrhrh
Field Bits Type Description
BS [3:0] rh Buffer Size
This bit field indicates the coded buffer size of the pipe x
Remote Window in the receiving controller. BS further
determines how many address offset bits are
transmitted in a Write Offset and Data Frame or in a
Discrete Read Frame. When register TPxBAR is written
for generation of a Copy Base Address Frame, BS is
updated by the Copy Base Address Frame (see
Page 23-26).
0000
B
1-bit offset address of Remote Window
0001
B
2-bit offset address of Remote Window
0010
B
3-bit offset address of Remote Window
…
B
…
1110
B
15-bit offset address of Remote Window
1111
B
16-bit offset address of Remote Window
DW [5:4] rh Data Width
This bit field indicates the data width that has been
detected for a read or write access of a bus master to a
Transfer Window of pipe x (see Page 23-28 and
Page 23-32).
00
B
8-bit data width detected
01
B
16-bit data width detected
10
B
32-bit data width detected
11
B
Reserved