TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-100 V2.0, 2007-07
MLI, V2.0
DVx
(x = 0-3)
16 + x rh Data Valid
Bit is set by hardware when the TPxDATAR and/or the
TPxAOFR registers of the MLI transmitter are updated
after a read or write access to a Transfer Window of
pipe x. DVx is cleared again by hardware when the
Read or Write Frame has been correctly sent. DVx can
be cleared by software via bit SCR.CDVx.
RPx
(x = 0-3)
20 + x rh Read Pending
Bit is set by hardware when the TPxAOFR register of
the MLI transmitter is updated after a read access to a
Transfer Window of pipe x. RPx is cleared by hardware
when the MLI receiver in the Local Controller receives
an Answer Frame for pipe x from the Remote
Controller. RPx can be cleared by software via bit
SCR.CDVx.
PN [25:24] rh Pipe Number
This bit field indicates the Pipe Number x of the base
address that has been written into register TPxBAR.
00
B
TP0BAR has been last written.
01
B
TP1BAR has been last written.
10
B
TP2BAR has been last written.
11
B
TP3BAR has been last written.
0 [3:0],
[15:10],
[31:26]
r Reserved
Read as 0.
Field Bits Type Description
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