Infineon Technologies TC1796 - Page 1615

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-106 V2.0, 2007-07
MLI, V2.0
NFSIRx
(x = 0-3)
16 + x w Normal Frame Sent in Pipe x Flag Clear
0
B
No action.
1
B
Clear TISR.NFSIx.
CFSIRx
(x = 0-3)
20 + x w Command Frame Sent in Pipe x Flag Clear
0
B
No action.
1
B
Clear TISR.CFSIx.
PEIR 24 w Parity Error Flag Clear
0
B
No action.
1
B
Clear TISR.PEIx.
TEIR 25 w Time Out Error Flag Clear
0
B
No action.
1
B
Clear TISR.TEIx.
0 [15:10],
[31:26]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description