EasyManua.ls Logo

Infineon Technologies TC1796 - Page 1618

Infineon Technologies TC1796
2150 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-109 V2.0, 2007-07
MLI, V2.0
NFSIP3 [14:12] rw Normal Frame Sent in Pipe 3 Interrupt Pointer
This bit field determines which service request output
SRx becomes active when a Normal Frame sent in
pipe 3 event occurs (if enabled). Coding see NFSIP0.
CFSIP [18:16] rw Command Frame Sent Interrupt Pointer
This bit field determines which service request output
SRx becomes active when a Command Frame sent
event occurs (if enabled). Coding see NFSIP0.
PTEIP [22:20] rw Parity or Time Out Interrupt Pointer
This bit field determines which service request output
SRx becomes active when a parity/time-out event
occurs (if enabled). Coding see NFSIP0.
0 3, 7,
11, 15,
19,
[31:23]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description

Table of Contents