Infineon Technologies TC1796 User Manual

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-118 V2.0, 2007-07
MLI, V2.0
ICE 6rwInterrupt Command Enable
This bit determines if an SRx output line is activated if a
Command Frame is received in pipe 0.
0
B
Command frame received in pipe 0 event is
disabled for activation of an SRx line.
1
B
Command frame received in pipe 0 event is
enabled for activation of an SRx line.
PEIE 7rwParity Error Interrupt Enable
This bit determines if an SRx output line is activated if
receiver a parity error event is detected.
0
B
Parity error event is disabled for activation of an
SRx line.
1
B
Parity error event is enabled for activation of an
SRx line.
MPEIE 8rwMemory Access Protection Interrupt Enable
This bit determines if an SRx output line is activated if a
memory access protection error is detected.
0
B
Memory access protection error event is disabled
for activation of an SRx line.
1
B
Memory access protection error event is enabled
for activation of an SRx line.
DRAIE 9rwDiscarded Read Answer Interrupt Enable
This bit determines if an SRx output line is activated if a
discarded read Answer Frame condition is detected.
0
B
Discarded read answer event is disabled for
activation of an SRx line.
1
B
Discarded read answer event is enabled for
activation of an SRx line.
NFRIR 16 w Normal Frame Received Interrupt Flag Clear
0
B
No action.
1
B
Clear RISR.NFRI.
MEIR 17 w MLI Move Engine Interrupt Flag Clear
0
B
No action.
1
B
Clear RISR.MEI.
CFRIRx
(x = 0-3)
18 + x w Command Frame Received in Pipe x Interrupt Flag
Clear
0
B
No action.
1
B
Clear RISR.CFRIx.
Field Bits Type Description

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English