Infineon Technologies TC1796 - Page 1628

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-119 V2.0, 2007-07
MLI, V2.0
ICER 22 w Interrupt Command Flag Clear
0
B
No action.
1
B
Clear RISR.ICE.
PEIR 23 w Parity Error Interrupt Flag Clear
0
B
No action.
1
B
Clear RISR.PEI.
MPEIR 24 w Memory Protection Error Interrupt Flag Clear
0
B
No action.
1
B
Clear RISR.MPEI.
DRAIR 25 w Discarded Read Answer Interrupt Flag Clear
0
B
No action.
1
B
Clear RISR.DRAI.
0 [15:10],
[31:26]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description