TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-125 V2.0, 2007-07
MLI, V2.0
Figure 23-51 MLI0 Module Implementation and Interconnections
When programming the MLI0_OICR register, the following additional items must be
considered:
• Unused transmitter/receiver output lines with index “C” (TVALIDC and RREADYC,
not shown in the figure above) are not connected.
• Unused transmitter/receiver input lines with index “C” (TREADYC, RCLKC,
RVALIDC, and RDATAC, not shown in the figure above) are connected to low level.
See also Page 23-130 for additional details on I/O line control and function selection.
SR[3:0]
f
MLI0
Address
Decoder
Interrupt
Control
Clock
Control
To DMA
SR[7:4]
Port 1
Control
P1.5 / TREADY0A
Port 5
Control
TREADYA
TCLK
TREADYD
TVALIDA
TVALIDD
TDATA
TransmitterReceiver
RCLKA
RCLKD
RREADYA
RREADYD
RVALIDA
RVALIDD
RDATAA
RDATAB
TREADYB
RREADYB
RVALIDB
RDATAD
TVALIDB
RCLKB
MLI0
Module
(Kernel)
MCA05906
P1.4 / TCLK0
P1.3 / TREADY0B
P1.6 / TVALID0A
P1.7 / TDATA0
P1.8 / RCLK0A
P1.9 / RREADY0A
P1.10 / RVALID0A
P1.11 / RDATA0A
P1.13 / RCLK0B
P1.14 / RVALID0B
P1.15 / RDATA0B
P5.4 / RREADY0B
P5.6 / TVALID0B
f
DMA
BRKOUT
Cerberus
A1
A2
A2
A2
A1
A1
A2
A1
A1
A1
A1
A1
A2
A2
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