Infineon Technologies TC1796 - Page 1641

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-132 V2.0, 2007-07
MLI, V2.0
MLI1 P8.0 / TCLK1 P8_IOCR0.PC0 = 1X11
B
1)
MLI1_OICR.TCE = 1
MLI1_OICR.TCP = X
2)
Output
P8.1 / TREADY1A P8_IOCR0.PC1 = 0XXX
B
1)
MLI1_OICR.TRE = 1
MLI1_OICR.TRP = X
2)
MLI1_OICR.TRS = 00
B
Input
P8.2 / TVALID1A P8_IOCR0.PC2 = 1X11
B
1)
MLI1_OICR.TVEA = 1
MLI1_OICR.TVPA = X
2)
Output
P8.3 / TDATA1 P8_IOCR0.PC3 = 1X11
B
1)
MLI1_OICR.TDP = X
2)
Output
P8.4 / RCLK1A P8_IOCR4.PC4 = 0XXX
B
1)
MLI1_OICR.RCE = 1
MLI1_OICR.RCP = X
2)
MLI1_OICR.RCS = 00
B
Input
P8.5 / RREADY1A P8_IOCR4.PC5 = 1X11
B
1)
MLI1_OICR.RRS = 00
B
MLI1_OICR.RRPA = X
2)
Output
P8.6 / RVALID1A P8_IOCR4.PC6 = 0XXX
B
1)
MLI1_OICR.RVE = 1
MLI1_OICR.RVP = X
2)
MLI1_OICR.RVS = 00
B
Input
P8.7 / RDATA1A P8_IOCR4.PC7 = 0XXX
B
1)
MLI1_OICR.RDP = X
2)
MLI1_OICR.RDS = 00
B
Input
1) Possible PCx bit field combinations see Table 23-12.
2) With polarity control bit = 0, normal polarity is selected. With polarity control bit = 1, inverted polarity is
selected.
Table 23-11 MLI0 and MLI1 I/O Line Selection and Setup (cont’d)
Module Port Lines Input/Output Control
Register Bits
I/O