TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-25 V2.0, 2007-07
GPTA, V2.0
The DCM unit inputs are connected to the PDL outputs. Depending on the configuration
of the associated PDL cell, the DCM units can also be driven by an FPC directly (as
shown in Figure 24-12):
• DCM0 is driven by FPC0 or PDL0 angular velocity signal,
• DCM1 is driven by FPC2 or PDL0 error signal,
• DCM2 is driven by FPC3 or PDL1 angular velocity signal,
• DCM3 is driven by FPC5 or PDL1 error signal.
When the driving FPCs and PDL cells are programmed in feed-through mode, an
external port pin signal as selected by the FPC input multiplexer can be directly
processed by a DCM cell.
The duty cycle of the DCM unit signal input can be determined by measuring its period
length and the width of its low or high state. For this purpose, several operations can be
started on an signal input edge:
• Reset Timer
The local timer can be reset on rising, falling, or both edges of the signal input line as
selected via control bits DCMCTRk.RZE (for rising edge) and DCMCTRk.FZE (for
falling edge). After a reset timer event, the timer is continuously incremented by the
GPTA module clock f
GPTA
until the next reset condition occurs. If no reset timer event
is enabled, the timer operates in Free-Running Timer Mode, repeatedly counting
from its lower limit (000000
H
) to its upper limit (FFFFFF
H
).
• Capture
The current timer value is stored in the capture register DCMCAV on the rising edge
(DCMCTR.RCA = 1) or falling edge (DCMCTRk.RCA = 0) of the signal input line.
The current timer value is stored in the capture/compare register DCMCOV on the
opposite signal edge as selected by DCMCTRk.RCA and if enabled by bit
DCMCTRk.OCA = 1. With DCMCTRk.OCA = 0 the capture/compare register
DCMCOV is not affected.
• Edge Service Request and Interrupt Request
On a rising input signal edge of the DCMk unit (k = 0-3) the service request flag
SRS0.DCM0kR is set. Additionally, a service request signal is triggered if bit
DCMCTRk.RRE = 1. A falling input signal edge sets the service request flag
SRS0.DCM0kF. An interrupt request generation on this edge is triggered if bit
DCMCTRk.FRE = 1. Both edges of the signal input line initiate an interrupt request
when both bits, DCMCTRk.FRE and DCMCTRk.RRE, are set. The interrupt on signal
input edges is disabled if both bits are cleared.
• Hardware Generated Output Pulse
A single f
GPTA
clock pulse is generated on the DCM output line if enabled by control
register bit DCMCTRk.RCK (rising edge at signal line) and/or DCMCTRk.FCK (falling
edge at signal line) and an appropriate edge is detected at the input.
The 0% or 100% duty cycle exception (no edge or only one edge detected) can be
handled by a limit checking option. The expected input signal’s maximum period
length (measured in f
GPTA
clock ticks) can be loaded into the capture/compare
To Next Page
Loading...
Need help?
General