Infineon Technologies TC1796 - Page 1832

TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-177 V2.0, 2007-07
GPTA, V2.0
0 9,
[31:16]
r Reserved
Read as 0; should be written with 0.
GPTA0_GTCCTRk (k = 00-31)
GPTA0 Global Timer Cell Control Register k [Compare Mode]
(100
H
+k*8
H
) Reset Value: 0000 0000
H
GPTA1_GTCCTRk (k = 00-31)
GPTA1 Global Timer Cell Control Register k [Compare Mode]
(100
H
+k*8
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
OUT OIA OCM CEN 0 EOA BYP CAT CAC GES REN OSM MOD
rh rw rw rh r rwh rw rw rw rw rw rw rw
Field Bits Type Description
MOD [1:0] rw Mode Control Bits
00
B
GTCk operates in Capture Mode hooked to GT0.
01
B
GTCk operates in Capture Mode hooked to GT1.
10
B
GTCk operates in Compare Mode hooked to GT0.
11
B
GTCk operates in Compare Mode hooked to GT1.
OSM 2rwOne Shot Mode Enable
0
B
GTCk is continuously enabled.
1
B
GTCk is enabled for one event only.
REN 3rwInterrupt Request Enable
0
B
Service request is disabled.
1
B
Service request line SQSk is activated when a
capture or compare event has occurred.
GES 4rwGreater Equal Select
0
B
An “equal” compare is selected.
1
B
A “greater equal” compare is required.
Field Bits Type Description