Infineon Technologies TC1796 - Page 1839

TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-184 V2.0, 2007-07
GPTA, V2.0
BYP 6rwBypass
0
B
M0O/M1O lines are affected either by M0I/M1I
lines or by OCM0/OCM1 bits.
1
B
M0O/M1O lines are affected only by M0I/M1I
lines.
This bit is cleared if mode is switched to Timer Mode.
OCM2 must be set in any case to enable reaction on
M0I/M1I change.
EOA 7rwhEnable On Action
0
B
LTCk is enabled for local events.
1
B
LTCk is disabled for local events. On an event on
the communication link via M0I/M1I lines, EOA
will be cleared and local events will be enabled.
EOA is bit protected (see Section 24.3.2). EOA is
cleared if mode is switched to Timer Mode.
ILM 8rwInput Line Mode
0
B
Input line is operating in Edge Sensitive Mode.
1
B
Input line is operating in Level Sensitive Mode.
In case of full speed GPTA module clock selection as
input clock, Level Sensitive Mode must be selected. In
this case the Edge Sensitive Mode will not produce any
event.
SLL 9rhCapture & Compare Mode: Select Line Level
0
B
Current state of select input SI is 0.
1
B
Current state of select input SI is 1.
CEN 10 rh Cell Enable
0
B
LTCk is currently disabled for local events.
1
B
LTCk is currently enabled for local events.
OCM [13:11] rw Output Control Mode Select
X00
B
Current state of LTCkOUT output line is hold.
X01
B
Current state of LTCkOUT output line is toggled.
X10
B
LTCkOUT output line is forced to 0.
X11
B
LTCkOUT output line is forced to 1.
0XX
B
LTCkOUT output line state is set by an internal
LTCk event only.
1XX
B
LTCkOUT output line state is affected by an
internal LTCk event and/or by an operation
occurred in an adjacent LTCk cell (reported by
M1I/M0I interface lines).
Field Bits Type Description