TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual 3-36 V2.0, 2007-07
Clock, V2.0
SC [13:12] rw Suspend Control
This bit field determines the behavior of the fractional
divider in suspend mode (bit SUSREQ and SUSACK
set).
00
B
Clock generation continues.
01
B
Clock generation is stopped and the clock
output signal is not generated. RESULT is not
changed except when writing bit field DM with
01
B
or 10
B
.
10
B
Clock generation is stopped and the clock
output signal is not generated. RESULT is
loaded with 3FF
H
.
11
B
Same as SC = 10
B
but signal Reset External
Divider is 1 (independently of bit field DM).
DM [15:14] rw Divider Mode
This bit fields determines the functionality of the
fractional divider block.
00
B
Fractional divider is switched off; no output
clock is generated. The Reset External Divider
signal is 1. RESULT is not updated (default
after reset).
01
B
Normal divider mode selected.
10
B
Fractional divider mode selected.
11
B
Fractional divider is switched off; no output
clock is generated. RESULT is not updated.
RESULT [25:16] rh Result Value
In normal divider mode, RESULT acts as reload
counter (addition +1).
In fractional divider mode, this bit field contains the
result of the addition RESULT + STEP.
If DM is written with 01
B
or 10
B
, RESULT is loaded
with 3FF
H
.
SUSACK 28 rh Suspend Mode Acknowledge
0
B
Suspend mode is not acknowledged.
1
B
Suspend mode is acknowledged.
Suspend mode is entered when SUSACK and
SUSREQ are set.
Field Bits Type Description
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