TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual 3-37 V2.0, 2007-07
Clock, V2.0
Note: See also Table 3-8 for further functional behavior of FDR bit fields and module
operation.
Note: The Fractional Divider Registers are Endinit-protected.
SUSREQ 29 rh Suspend Mode Request
0
B
Suspend mode is not requested.
1
B
Suspend mode is requested.
Suspend mode is entered when SUSREQ and
SUSACK are set.
ENHW 30 rw Enable Hardware Clock Control
0
B
Bit DISCLK cannot be cleared by hardware by
a high level of the External Clock Enable input
signal.
1
B
Bit DISCLK is cleared by hardware while the
External Clock Enable input signal is at high
level.
DISCLK 31 rwh Disable Clock
0
B
Clock generation of f
OUT
is enabled according
to the setting of bit field DM.
1
B
Fractional divider is stopped. Signal f
OUT
becomes inactive. No change except when
writing bit field DM.
In case of a conflict between hardware clearing and
software setting of DISCLK, the software setting
wins. Any write or read-modify-write action leads to
the described behavior. As a result, read-modify-
write operations should be avoided.
0 10,
[27:26]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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