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Infineon Technologies TC1796 User Manual
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TC1796
Peripheral Un
its (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s M
anual
24-216
V2.0, 20
07-07
GPTA, V2
.0
0
[31:16]
r
Reserved
Read as 0; shoul
d be wri
tten with 0.
Field
Bits
Type
Description
1870
1872
Table of Contents
Table of Contents
9
System Units (Vol. 1 of 2)
9
Peripheral Units (Vol. 2 of 2)
28
1 Introduction
40
1.1 About this Document
40
1.1.1 Related Documentations
40
1.1.2 Text Conventions
40
1.1.3 Reserved, Undefined, and Unimplemented Terminology
42
1.1.4 Register Access Modes
43
1.1.5 Abbreviations and Acronyms
44
1.2 System Architecture of the TC1796
47
1.2.1 TC1796 Block Diagram
48
1.2.2 Features
49
1.3 On-Chip Peripheral Units of the TC1796
53
1.3.1 Serial Interfaces
53
1.3.1.1 Asynchronous/Synchronous Serial Interfaces
54
1.3.1.2 High-Speed Synchronous Serial Interfaces
56
1.3.1.3 Micro Second Channel Interfaces
58
1.3.1.4 MultiCAN Controller
60
1.3.1.5 Micro Link Serial Bus Interface
63
1.3.2 General Purpose Timer Array
65
1.3.2.1 Functionality of GPTA0 and GPTA1
66
1.3.2.2 Functionality of LTCA2
68
1.3.3 Analog-to-Digital Converters
69
1.3.3.1 Analog-to-Digital Converters (ADC0 and ADC1)
69
1.3.3.2 Fast Analog-to-Digital Converter Unit (FADC)
71
1.4 TC1796 Pin Definitions and Functions
73
1.4.1 TC1796 Pin Configuration
74
1.4.2 Pad Driver Classes Overview
96
1.4.3 Pull-Up/Pull-Down Behavior of the Pins
97
2 CPU Subsystem
98
2.1 TC1796 Processor Subsystem
98
2.2 Central Processing Unit Features
99
2.2.1 CPU Diagram
100
2.2.2 Instruction Fetch Unit
101
2.2.3 Execution Unit
102
2.2.4 General Purpose Register File
103
2.3 Implementation-specific Features
104
2.3.1 Context Save Areas
104
2.3.2 Fast Context Switching
104
2.3.3 Reset System
104
2.3.4 Program Counter Register - PC
104
2.3.5 Interrupt System
105
2.3.6 Trap System
105
2.4 TC1796 CPU Subsystem Registers
106
2.4.1 Core Special Function Registers (CSFR)
107
2.4.1.1 Implementation-specific Core Special Function Registers
108
2.4.2 CPU Slave Interface (CPS) Registers
110
2.4.2.1 Implementation-specific CPU Slave Interface Registers
111
2.4.3 CPU General Purpose Registers
112
2.4.4 Core Debug Registers
114
2.4.4.1 Implementation-specific Core Debug Registers
115
2.4.5 Memory Protection Registers
117
2.4.5.1 Implementation-specific Memory Protection Registers
120
2.5 Program Memory Interface (PMI)
121
2.5.1 PMI Features
121
2.5.2 Parity Protection for PMI Memories
122
2.5.3 PMI Registers
123
2.5.3.1 PMI Module Identification Register
124
2.5.3.2 PMI Control Register 0
125
2.5.3.3 PMI Control Register 1
126
2.5.3.4 PMI Control Register 2
127
2.6 Data Memory Interface (DMI)
128
2.6.1 DMI Features
128
2.6.2 Dual-Ported Memory Operation
129
2.6.2.1 CPU Buffer Write Operation
129
2.6.3 Parity Protection for DMI Memories
130
2.6.4 DMI Registers
131
2.6.4.1 DMI Register Description
132
2.7 Instruction Timing
137
2.7.1 Integer-Pipeline Instructions
138
2.7.1.1 Simple Arithmetic Instruction Timings
138
2.7.1.2 Multiply Instruction Timings
142
2.7.1.3 MAC Instruction Timings
143
2.7.1.4 Control Flow Instruction Timing
144
2.7.2 Load-Store Pipeline Instructions
145
2.7.2.1 Address Arithmetic Timing
145
2.7.2.2 Control Flow Instruction Timing
146
2.7.2.3 Load Instruction Timing
147
2.7.2.4 Store Instruction Timing
148
2.8 Floating Point Pipeline Timings
149
3 Clock System and Control
150
3.1 Overview
150
3.2 Clock Generation Unit
152
3.2.1 Main Oscillator Circuit
153
3.2.1.1 Oscillator Bypass Mode
154
3.2.1.2 Oscillator Run Detection
155
3.2.1.3 Oscillator Gain Control
156
3.2.1.4 Oscillator Control Register
157
3.2.2 Phase Looked Loop (PLL) Circuitry
159
3.2.2.1 Clock Source Control
159
3.2.2.2 PLL Parameters
161
3.2.2.3 PLL Clock Control and Status Register
165
3.2.2.4 Changing PLL Parameters
167
3.2.2.5 Setting up the PLL after Reset
167
3.2.2.6 Lock Detection
168
3.2.2.7 Loss-of-Lock Recovery
168
3.2.3 Power-on Startup Operation
170
3.3 Module Power Management and Clock Gating
171
3.3.1 Module Clock Generation
172
3.3.2 Clock Control Register CLC
173
3.3.3 Fractional Divider Operation
178
3.3.3.1 Overview
178
3.3.3.2 Fractional Divider Operating Modes
181
3.3.3.3 Fractional Divider Register
184
3.3.4 Module Clock Register Implementations
188
3.3.5 Fractional Divider Register Implementations
189
3.4 System Clock Output Control
190
3.4.1 System Clock Fractional Divider Register
191
4 Reset and Boot Operation
193
4.1 Reset and Boot Overview
193
4.1.1 Reset Status and Control Registers
195
4.1.1.1 Reset Status Register
195
4.1.1.2 Reset Request Register
197
4.2 Reset Operations
199
4.2.1 Power-On Reset
199
4.2.2 External Hardware Reset
199
4.2.3 Software Reset
200
4.2.4 Watchdog Timer Reset
200
4.2.5 Debug System Reset
202
4.2.6 Module Reset Behavior
202
4.2.7 Booting Scheme
204
4.2.7.1 Normal Boot Options
206
4.2.7.2 Debug Boot Options
207
4.3 Boot ROM
208
4.3.1 Addressing
208
4.3.2 Program Structure
208
4.3.3 Initial State after Boot ROM Exit
211
4.4 Bootstrap Loader (BSL)
212
4.4.1 Bootstrap Loader Mode 1 - ASC Boot via ASC0 Pins
213
4.4.2 Bootstrap Loader Mode 2 - CAN Boot via CAN Pins
216
4.4.3 Bootstrap Loader Mode 3 - ASC Boot via CAN Pins
220
4.4.4 Alternate Boot Modes
220
5 System Control Unit
223
5.1 Power Management
224
5.1.1 Power Management Overview
224
5.1.2 Power Management Control and Status Register, PMG_CSR
225
5.1.3 Power Management Modes
227
5.1.3.1 Idle Mode
227
5.1.3.2 Sleep Mode
228
5.1.3.3 States of TC1796 Units in Power Management Modes
229
5.2 Configuration Input Sampling
230
5.3 External Request Unit (ERU)
231
5.3.1 Input Channel
232
5.3.2 Output Channel
234
5.3.3 External Request Unit Implementation
236
5.3.4 External Request Unit Registers
238
5.4 Special System Interrupts
257
5.4.1 FPU Interrupts
257
5.4.2 Flash Interrupt
258
5.4.3 External Interrupts
258
5.5 SRAM Parity Control
259
5.5.1 Parity Error Trap Registers
261
5.6 Pad Driver Temperature Compensation Control
263
5.6.1 Functional Description
263
5.6.2 Temperature Compensation Registers
266
5.7 Die Temperature Sensor
270
5.8 GPTA1 Input IN1 Control
271
5.9 Pad Test Mode Control
272
5.9.1 Pad Test Mode Enabling
273
5.9.2 Pad Test Mode Registers
273
5.10 Emergency Stop Output Control for GPTA and MSC
279
5.10.1 GPTA Output Emergency Control in the GPIO Ports
280
5.10.2 MSC Emergency Control Selection
280
5.10.3 Emergency Stop Register
281
5.11 Analog Input 7 Testmode
282
5.12 SCU Registers and Address Map
283
5.13 Miscellaneous SCU Registers
286
5.13.1 SCU Control Register
286
5.13.2 SCU Status Register
289
5.13.3 Device Identification Registers
291
6 On-Chip System Buses and Bus Bridges
294
6.1 Program and Data Local Memory Buses
295
6.1.1 Overview
295
6.1.2 Transaction Types
296
6.1.2.1 Single Transfers
296
6.1.2.2 Block Transfers
296
6.1.2.3 Atomic Transfers
296
6.1.3 Address Alignment Rules
296
6.1.4 Reaction of a Busy Slave
296
6.1.5 LMB Basic Operation
297
6.2 Local Memory Bus Controller Units
298
6.2.1 Basic Operation
298
6.2.2 LMB Bus Arbitration
298
6.2.2.1 LMB Bus Default Master
299
6.2.3 LMB Bus Error Handling
299
6.2.4 DLMB and PLMB Bus Registers
300
6.3 Local Memory to FPI Bus Interface (LFI Bridge)
308
6.3.1 Functional Overview
308
6.3.2 LFI Register
309
6.4 System and Remote Peripheral Bus
312
6.4.1 Overview
312
6.4.2 Bus Transaction Types
314
6.4.3 Reaction of a Busy Slave
314
6.4.4 Address Alignment Rules
315
6.4.5 FPI Bus Basic Operations
315
6.5 FPI Bus Control Units (SBCU and RBCU)
317
6.5.1 FPI Bus Arbitration
317
6.5.1.1 Arbitration on the System Peripheral Bus
317
6.5.1.2 Arbitration on the Remote Peripheral Bus
317
6.5.1.3 Starvation Prevention
318
6.5.2 FPI Bus Error Handling
318
6.5.3 Clock Management
320
6.5.4 BCU Debug Support
321
6.5.4.1 Address Triggers
321
6.5.4.2 Signal Status Triggers
322
6.5.4.3 Grant Triggers
322
6.5.4.4 Combination of Triggers
323
6.5.4.5 BCU Breakpoint Generation Examples
324
6.5.5 SBCU and RBCU Registers
327
6.5.5.1 BCU Control Registers
329
6.5.5.2 BCU Error Registers
331
6.5.5.3 OCDS Registers
335
6.5.5.4 BCU Service Request Control Register
351
7 Program Memory Unit
352
7.1 Boot ROM
352
7.2 Program & Data Flash Memory
353
7.2.1 Program Flash Overview
355
7.2.2 Data Flash Overview
358
7.2.3 User Configuration Blocks Overview
360
7.2.4 Basic Flash Operating Modes
362
7.2.4.1 Read Mode
362
7.2.4.2 Command Mode
363
7.2.4.3 Page Mode
364
7.2.5 Command Sequence Definitions
365
7.2.5.1 Reset-to-Read Command
366
7.2.5.2 Enter Page Mode Command
366
7.2.5.3 Load Page Buffer Command
367
7.2.5.4 Write Page Command
369
7.2.5.5 Write User Configuration Page Command
370
7.2.5.6 Erase Sector Command
371
7.2.5.7 Erase User Configuration Block Command
373
7.2.5.8 Disable Write Protection Command
374
7.2.5.9 Disable Read Protection Command
375
7.2.5.10 Resume Protection Command
375
7.2.5.11 Clear Status Command
376
7.2.6 Data Flash and EEPROM Emulation
377
7.2.7 Read and Write Protection
378
7.2.7.1 User Configuration Block Definitions
378
7.2.7.2 Write and OTP Protection for PFLASH
381
7.2.7.3 Read Protection for PFLASH and DFLASH
383
7.2.7.4 Password Check Control
384
7.2.8 Error Correction and Margin Control
385
7.2.8.1 Dynamic Error Correction
385
7.2.8.2 Margin Check Control
386
7.2.9 Flash Interrupt Generation and Control
387
7.2.10 Flash Power Supply, Power Saving and Reset
389
7.2.10.1 Power Supply
389
7.2.10.2 Sleep Mode
389
7.2.10.3 Shut-Down Mode
389
7.2.10.4 Reset Control
390
7.2.11 Flash Registers
391
7.2.11.1 Flash and PMU Module Identification Registers
392
7.2.11.2 Flash Status Register
394
7.2.11.3 Margin Control Registers
402
7.2.11.4 Flash Configuration Register
404
7.2.11.5 Protection Configuration Registers
410
7.3 Emulation Interface
412
8 Data Memory Unit
413
8.1 DLMB/PLMB Interfaces
414
8.2 SBRAM
414
8.3 SRAM
414
8.4 Parity Protection for DMU Memories
415
8.5 Data Access Overlay Functionality
415
8.5.1 Internal Overlay
419
8.5.2 Emulation Memory Overlay
419
8.5.3 Switching between Internal and Emulation Memory Overlay
419
8.5.4 Region Priority
419
8.5.5 Access Performance
419
8.6 Program Local Memory Bus Interface (LMI)
420
8.6.1 Data Read Buffer
420
8.7 DMU Registers
422
9 Memory Maps
431
9.1 How to Read the Address Maps
431
9.2 Contents of the Segments
434
9.3 Address Map of the FPI Bus System
436
9.3.1 Segments 0 to 14
436
9.3.2 Segment 15
440
9.4 Address Map of the Program Local Memory Bus (PLMB)
445
9.5 Address Map of the Data Local Memory Bus (DLMB)
449
9.6 Memory Module Access Restrictions
452
10 General Purpose I/O Ports and Peripheral I/O Lines
453
10.1 Basic Port Operation
454
10.2 Port Register Description
457
10.2.1 Port Input/Output Control Registers
459
10.2.2 Pad Driver Mode Register
462
10.2.3 Port Output Register
465
10.2.4 Port Output Modification Register
466
10.2.5 Emergency Stop Register
468
10.2.6 Port Input Register
469
10.3 Port 0
470
10.3.1 Port 0 Configuration
470
10.3.2 Port 0 Function Table
471
10.3.3 Port 0 Registers
474
10.3.3.1 Port 0 Pad Driver Mode Register and Pad Classes
475
10.3.3.2 Port 0 Software Configuration Selection
476
10.3.3.3 Reserved SWOPT Bits of SCU_SCLIR Register
477
10.4 Port 1
478
10.4.1 Port 1 Configuration
478
10.4.2 Port 1 Function Table
479
10.4.3 Port 1 Registers
482
10.4.3.1 Port 1 Pad Driver Mode Register and Pad Classes
483
10.5 Port 2
484
10.5.1 Port 2 Configuration
484
10.5.2 Port 2 Function Table
485
10.5.3 Port 2 Registers
489
10.5.3.1 Port 2 Output Register
489
10.5.3.2 Port 2 Output Modification Register
489
10.5.3.3 Port 2 Input/Output Control Register 0
490
10.5.3.4 Port 2 Input Register
490
10.5.3.5 Port 2 Emergency Stop Register
490
10.5.3.6 Port 2 Pad Driver Mode Register and Pad Classes
491
10.6 Port 3
492
10.6.1 Port 3 Configuration
492
10.6.2 Port 3 Function Table
493
10.6.3 Port 3 Registers
497
10.6.3.1 Port 3 Pad Driver Mode Register and Pad Classes
498
10.7 Port 4
499
10.7.1 Port 4 Configuration
499
10.7.2 Port 4 Function Table
500
10.7.3 Port 4 Registers
503
10.7.3.1 Port 4 Pad Driver Mode Register and Pad Classes
505
10.8 Port 5
506
10.8.1 Port 5 Configuration
506
10.8.2 Port 5 Function Table
507
10.8.3 Port 5 Registers
509
10.8.3.1 Port 5 Output Register
509
10.8.3.2 Port 5 Output Modification Register
509
10.8.3.3 Port 5 Input Register
509
10.8.3.4 Port 5 Pad Driver Mode Register and Pad Classes
510
10.9 Port 6
511
10.9.1 Port 6 Configuration
511
10.9.2 Port 6 Function Table
512
10.9.3 Port 6 Registers
515
10.9.3.1 Port 6 Output Register
515
10.9.3.2 Port 6 Output Modification Register
515
10.9.3.3 Port 6 Input Register
515
10.9.3.4 Port 6 Pad Driver Mode Register and Pad Classes
516
10.10 Port 7
517
10.10.1 Port 7 Configuration
517
10.10.2 Port 7 Function Table
518
10.10.3 Port 7 Registers
520
10.10.3.1 Port 7 Output Register
520
10.10.3.2 Port 7 Output Modification Register
520
10.10.3.3 Port 7 Input Register
520
10.10.3.4 Port 7 Pad Driver Mode Register and Pad Classes
521
10.11 Port 8
522
10.11.1 Port 8 Configuration
522
10.11.2 Port 8 Function Table
523
10.11.3 Port 8 Register
525
10.11.3.1 Port 8 Output Register
525
10.11.3.2 Port 8 Output Modification Register
525
10.11.3.3 Port 8 Input Register
525
10.11.3.4 Port 8 Emergency Stop Register
525
10.11.3.5 Port 8 Pad Driver Mode Register and Pad Classes
526
10.12 Port 9
527
10.12.1 Port 9 Configuration
527
10.12.2 Port 9 Function Table
528
10.12.3 Port 9 Register
530
10.12.3.1 Port 9 Output Register
530
10.12.3.2 Port 9 Output Modification Register
530
10.12.3.3 Port 9 Input/Output Control Register 8
531
10.12.3.4 Port 9 Input Register
531
10.12.3.5 Port 9 Emergency Stop Register
531
10.12.3.6 Port 9 Pad Driver Mode Register and Pad Classes
532
10.13 Port 10 (Hardware Select Inputs)
533
10.13.1 Port 10 Configuration
533
10.13.2 Port 10 Registers
534
10.13.2.1 Port 10 Input Register
534
10.14 Dedicated Peripheral I/O Lines
535
10.14.1 Dedicated I/O Lines for SSC0 and SSC1
535
10.14.2 LVDS Outputs of MSC0 and MSC1
537
11 Peripheral Control Processor (PCP)
538
11.1 Peripheral Control Processor Overview
538
11.2 PCP Architecture
539
11.2.1 PCP Processor
540
11.2.2 PCP Code Memory
541
11.2.3 PCP Parameter RAM
541
11.2.4 FPI Bus Interface
541
11.2.5 PCP Interrupt Control Unit and Service Request Nodes
542
11.3 PCP Programming Model
543
11.3.1 General Purpose Register Set of the PCP
543
11.3.1.1 Register R0
544
11.3.1.2 Registers R1, R2, and R3
544
11.3.1.3 Registers R4 and R5
544
11.3.1.4 Register R6
545
11.3.1.5 Register R7
546
11.3.2 Contexts and Context Models
548
11.3.2.1 Context Models
548
11.3.2.2 Context Save Area
551
11.3.2.3 Context Restore Operation for CR6 and CR7
554
11.3.2.4 Context Save Operation for CR6 and CR7
558
11.3.2.5 Initialization of the Contexts
561
11.3.2.6 Context Save Optimization
561
11.3.3 Channel Programs
562
11.3.3.1 Channel Restart Mode
562
11.3.3.2 Channel Resume Mode
563
11.4 PCP Operation
565
11.4.1 PCP Initialization
565
11.4.2 Channel Invocation and Context Restore Operation
565
11.4.3 Channel Exit and Context Save Operation
566
11.4.3.1 Normal Exit
566
11.4.3.2 Error Condition Channel Exit
567
11.4.3.3 Debug Exit
568
11.5 PCP Interrupt Operation
569
11.5.1 Issuing Service Requests to CPU or PCP
569
11.5.2 PCP Interrupt Control Unit
570
11.5.3 PCP Service Request Nodes
570
11.5.4 Issuing PCP Service Requests
571
11.5.4.1 Service Request on EXIT Instruction
572
11.5.4.2 Service Request on Suspension of Interrupt
572
11.5.4.3 Service Request on Error
573
11.5.4.4 Queue Full Operation
573
11.6 PCP Error Handling
575
11.6.1 Enforced PRAM Partitioning
575
11.6.2 Channel Watchdog
576
11.6.3 Invalid Opcode
576
11.6.4 Instruction Address Error
576
11.7 Instruction Set Overview
577
11.7.1 DMA Primitives
577
11.7.2 Load and Store
578
11.7.3 Arithmetic and Logical Instructions
579
11.7.4 Bit Manipulation
581
11.7.5 Flow Control
581
11.7.6 Addressing Modes
582
11.7.6.1 FPI Bus Addressing
582
11.7.6.2 PRAM Addressing
583
11.7.6.3 Bit Addressing
583
11.7.6.4 Flow Control Destination Addressing
583
11.8 Accessing PCP Resources from the FPI Bus
585
11.8.1 Access to the PCP Control Registers
585
11.8.2 Access to the PRAM
585
11.8.3 Access to the CMEM
586
11.9 Debugging the PCP
587
11.10 PCP Registers
589
11.10.1 Module Identification Register, PCP_ID
591
11.10.2 PCP Clock Control Register, PCP_CLC
592
11.10.3 PCP Control and Status Register, PCP_CS
593
11.10.4 PCP Error/Debug Status Register, PCP_ES
596
11.10.5 PCP Interrupt Control Register, PCP_ICR
598
11.10.6 PCP Interrupt Threshold Register, PCP_ITR
600
11.10.7 PCP Interrupt Configuration Register, PCP_ICON
601
11.10.8 PCP Stall Status Register, PCP_SSR
603
11.10.9 PCP Service Request Control Registers, PCP_SRC[1:0]
604
11.10.10 PCP Service Request Control Registers, PCP_SRC[3:2]
605
11.10.11 PCP Service Request Control Registers, PCP_SRC[8:4]
606
11.10.12 PCP Service Request Control Registers, PCP_SRC[11:9]
607
11.11 PCP Instruction Set Details
609
11.11.1 Instruction Codes and Fields
609
11.11.1.1 Conditional Codes
610
11.11.1.2 Instruction Fields
611
11.11.2 Counter Operation for COPY Instruction
614
11.11.3 Counter Operation for BCOPY Instruction
615
11.11.4 Divide and Multiply Instructions
616
11.11.5 ADD, 32-Bit Addition
617
11.11.6 BCOPY, DMA Operation
618
11.11.7 AND, 32-Bit Logical AND
619
11.11.8 CHKB, Check Bit
620
11.11.9 CLR, Clear Bit
620
11.11.10 COMP, 32-Bit Compare
621
11.11.11 COPY, DMA Instruction
622
11.11.12 DEBUG, Debug Instruction
623
11.11.13 DINIT, Divide Initialization Instruction
624
11.11.14 DSTEP, Divide Instruction
625
11.11.15 INB, Insert Bit
625
11.11.16 EXIT, Exit Instruction
626
11.11.17 JC, Jump Conditionally
627
11.11.18 JL, Jump Long Unconditional
628
11.11.19 LD, Load
628
11.11.20 LDL, Load 16-bit Value
630
11.11.21 Multiply Initialization Instruction
630
11.11.22 MOV, Move Register to Register
631
11.11.23 Multiply Instructions
632
11.11.24 NEG, Negate
633
11.11.25 NOP, No Operation
633
11.11.26 NOT, Logical NOT
633
11.11.27 OR, Logical OR
634
11.11.28 PRI, Prioritize
635
11.11.29 PRAM Bit Operations
636
11.11.30 RL, Rotate Left
637
11.11.31 RR, Rotate Right
637
11.11.32 SET, Set Bit
638
11.11.33 SHL, Shift Left
638
11.11.34 SHR, Shift Right
639
11.11.35 ST, Store
640
11.11.36 SUB, 32-Bit Subtract
641
11.11.37 XCH, Exchange
642
11.11.38 XOR, 32-Bit Logical Exclusive OR
643
11.11.39 Flag Updates of Instructions
644
11.11.40 Instruction Timing
645
11.12 Programming of the PCP
649
11.12.1 Initial PC of a channel program
649
11.12.1.1 Channel Entry Table
649
11.12.1.2 Channel Resume
650
11.12.2 Channel Management for Small and Minimum Contexts
651
11.12.3 Unused Registers as Globals or Constants
651
11.12.4 Dispatch of Low Priority Tasks
652
11.12.5 Code Reuse Across Channels (Call and Return)
652
11.12.6 Case-like Code Switches (Computed Go-To)
653
11.12.7 Simple DMA Operation
653
11.12.7.1 COPY Instruction
653
11.12.7.2 BCOPY Instruction (Burst Copy)
654
11.13 PCP Programming Notes and Tips
655
11.13.1 Notes on PCP Configuration
655
11.13.2 General Purpose Register Use
656
11.13.3 Use of Channel Interruption
657
11.13.3.1 Dynamic Interrupt Masking
657
11.13.3.2 Control of Channel Priority (CPPN)
657
11.13.4 Implementing Divide Algorithms
659
11.13.5 Implementing Multiply Algorithms
660
11.14 Implementation of the PCP in the TC1796
662
11.14.1 PCP Memories
662
11.14.2 Parity Protection for PCP Memories
662
11.14.3 PCP Reset Operation
663
11.14.4 BCOPY Instruction
664
12 Direct Memory Access Controller
665
12.1 DMA Controller Kernel Description
666
12.1.1 Features
667
12.1.2 Definition of Terms
668
12.1.3 DMA Principles
669
12.1.4 DMA Channel Functionality
670
12.1.4.1 Shadowed Source or Destination Address
670
12.1.4.2 DMA Channel Request Control
674
12.1.4.3 DMA Channel Operation Modes
675
12.1.4.4 Error Conditions
679
12.1.4.5 Channel Reset Operation
680
12.1.4.6 Transfer Count and Move Count
681
12.1.4.7 Circular Buffer
683
12.1.5 Transaction Control Engine
684
12.1.6 Bus Switch
685
12.1.7 On-Chip Debug Capabilities
687
12.1.7.1 Hard-suspend Mode
687
12.1.7.2 Soft-suspend Mode
687
12.1.7.3 Break Signal Generation
688
12.1.7.4 Trace Signal Generation
689
12.1.8 Interrupts
691
12.1.8.1 Channel Interrupts
691
12.1.8.2 Transaction Lost Interrupt
693
12.1.8.3 Move Engine Interrupts
694
12.1.8.4 Wrap Buffer Interrupts
696
12.1.8.5 Interrupt Request Compressor
697
12.1.9 Pattern Detection
698
12.1.9.1 Pattern Compare Logic
699
12.1.9.2 Pattern Detection for 8-bit Data Width
700
12.1.9.3 Pattern Detection for 16-bit Data Width
701
12.1.9.4 Pattern Detection for 32-bit Data Width
703
12.1.9.5 Access Protection
704
12.2 DMA Module Kernel Registers
706
12.2.1 System Registers
709
12.2.2 General Control/Status Registers
715
12.2.3 Move Engine Registers
733
12.2.4 Channel Control/Status Registers
740
12.2.5 Channel Address Registers
752
12.3 DMA Module Implementation
755
12.3.1 DMA Request Wiring Matrix
756
12.3.2 Access Protection Assignment
762
12.3.3 Implementation-specific DMA Registers
767
12.3.3.1 Clock Control Register
769
12.3.3.2 DMA Service Request Control Registers
770
12.3.3.3 MLI Service Request Control Registers
771
12.3.3.4 System Interrupt Service Request Control Register
772
12.3.4 DMA Controller Address Map
773
12.4 Memory Checker Module
774
12.4.1 Functional Description
774
12.4.2 Registers
775
12.4.2.1 Memory Checker Registers
776
13 LMB External Bus Unit
779
13.1 Block Diagram
780
13.2 EBU Interface Signals
781
13.2.1 Data Bus, D[31:0]
781
13.2.2 Address Bus, A[23:0]
782
13.2.3 Chip Selects, CS[3:0], CSCOMB
782
13.2.4 Burst Flash Clock Output/Input, BFCLKO/BFCLKI
782
13.2.5 Read/Write Control Lines, RD, RD/WR and MR/W
782
13.2.6 Address Valid, ADV
783
13.2.7 Byte Controls, BC[3:0]
783
13.2.8 Wait Input, WAIT
784
13.2.9 Burst Address Advance, BAA
784
13.2.10 Bus Arbitration Signals, HOLD, HLDA, and BREQ
784
13.2.11 EBU Power Supply
784
13.3 External Bus Arbitration
785
13.3.1 External Bus Modes
785
13.3.2 Arbitration Signals and Parameters
785
13.3.3 Arbitration Modes
788
13.3.3.1 No Bus Arbitration Mode
788
13.3.3.2 Sole Master Arbitration Mode
788
13.3.3.3 Arbiter Mode Arbitration Mode
788
13.3.3.4 “Participant Mode” Arbitration Mode
792
13.3.4 Arbitration Input Signal Sampling
795
13.3.5 Locking the External Bus
795
13.3.6 Reaction to an PLMB Access to the External Bus
796
13.3.6.1 Pending Access Time-Out
797
13.4 Start-Up/Boot Process
798
13.4.1 Disabled
798
13.4.2 Emulation Mode
798
13.4.3 External Boot Mode
799
13.4.3.1 Boot Process
799
13.4.3.2 Boot Configuration Value
801
13.5 Master Mode Operation
803
13.5.1 External Memory Regions
804
13.5.2 Chip Select Control
806
13.5.3 Address Comparison
808
13.5.4 Access Parameter Selection
813
13.5.5 Little-/Big-Endian Access Modes
814
13.5.6 PLMB Bus Width Translation
815
13.5.7 Address Alignment During Bus Accesses
816
13.6 PLMB Data Buffering
817
13.6.1 Data Read Buffer
817
13.6.2 Code Prefetch Buffer
818
13.6.3 Data Write Buffer
818
13.7 Standard Access Phases
819
13.7.1 Address Phase (AP)
819
13.7.2 Command Delay Phase (CD)
821
13.7.3 Command Phase (CP)
821
13.7.4 Data Hold Phase (DH)
823
13.7.5 Burst Phase (BP)
824
13.7.6 Recovery Phase (RP)
825
13.7.7 Multiplication Factor for Access Phase Length
827
13.8 Asynchronous Read/Write Accesses
828
13.8.1 Signal List
828
13.8.2 Demultiplexed Device Configurations
829
13.8.3 Standard Asynchronous Access Phases
831
13.8.4 Programmable Parameters
831
13.8.5 Accesses to Demultiplexed Devices
833
13.8.6 Dynamic Command Delay and Wait State Insertion
835
13.8.6.1 External Extension of the Command Phase by WAIT
835
13.8.6.2 Interfacing to INTEL-style Devices
839
13.8.6.3 Interfacing to Motorola-style Devices
841
13.9 Burst Mode Read Accesses
843
13.9.1 Signal List
843
13.9.2 Burst Flash Memory Configurations
844
13.9.3 Burst Mode Access Phases
846
13.9.4 Programmable Parameters
846
13.9.5 Support for two Burst Flash Device Types
849
13.9.6 BFCLKO Output
849
13.9.7 BFCLKI Input and Burst Flash Clock Feedback
850
13.9.8 Burst Length Control
851
13.9.9 Control of ADV and BAA Delays During Burst Flash Access
851
13.9.10 Burst Flash Access Cycle
852
13.9.11 External Cycle Control via the WAIT Input
853
13.9.11.1 Wait for Page Load Mode
854
13.9.11.2 Terminate and Start New Burst Mode
855
13.9.12 Termination of a Burst Mode Read Access
856
13.10 EBU Registers
857
13.10.1 Identification Register, ID
859
13.10.2 Clock Control Register, CLC
860
13.10.3 Configuration Register, CON
861
13.10.4 Burst Flash Control Register, BFCON
864
13.10.5 Address Select Register, ADDRSELx
868
13.10.6 Bus Configuration Register, BUSCONx
870
13.10.7 Bus Access Parameter Register, BUSAPx
875
13.10.8 Emulator Address Select Register, EMUAS
879
13.10.9 Emulator Bus Configuration Register, EMUBC
880
13.10.10 Emulator Bus Access Parameter Register, EMUBAP
884
13.10.11 Emulator Overlay Register, EMUOVL
888
13.10.12 Test/Control Configuration Register, USERCON
889
14 Interrupt System
890
14.1 Overview
890
14.2 Service Request Nodes
892
14.2.1 Service Request Control Registers
892
14.2.1.1 General Service Request Control Register Layout
893
14.2.1.2 Request Set and Clear Bits (SETR, CLRR)
894
14.2.1.3 Enable Bit (SRE)
894
14.2.1.4 Service Request Flag (SRR)
895
14.2.1.5 Type-Of-Service Control (TOS)
895
14.2.1.6 Service Request Priority Number (SRPN)
896
14.3 Interrupt Control Units
897
14.3.1 Interrupt Control Unit (ICU)
897
14.3.1.1 ICU Interrupt Control Register (ICR)
897
14.3.1.2 Operation of the Interrupt Control Unit (ICU)
899
14.3.2 PCP Interrupt Control Unit (PICU)
900
14.4 Arbitration Process
901
14.4.1 Controlling the Number of Arbitration Cycles
901
14.4.2 Controlling the Duration of Arbitration Cycles
902
14.5 Entering an Interrupt Service Routine
902
14.6 Exiting an Interrupt Service Routine
903
14.7 Interrupt Vector Table
904
14.8 Usage of the TC1796 Interrupt System
907
14.8.1 Spanning Interrupt Service Routines Across Vector Entries
907
14.8.2 Configuring Ordinary Interrupt Service Routines
908
14.8.3 Interrupt Priority Groups
908
14.8.4 Splitting Interrupt Service Across Different Priority Levels
909
14.8.5 Using different Priorities for the same Interrupt Source
910
14.8.6 Interrupt Priority 1
911
14.8.7 Software-Initiated Interrupts
911
14.8.8 External Interrupts
911
14.9 Service Request Node Table
912
14.10 Non-Maskable Interrupt
914
14.10.1 External NMI Input
914
14.10.2 Phase-Locked Loop NMI
914
14.10.3 Watchdog Timer NMI
914
14.10.4 SRAM Parity Error NMI
915
14.10.5 NMI Enable
916
14.10.6 NMI Status Register
916
15 System Timer
918
15.1 Overview
918
15.2 Operation
918
15.2.1 Resolution and Ranges
921
15.2.2 Compare Register Operation
922
15.2.3 Compare Match Interrupt Control
923
15.3 Kernel Registers
924
15.3.1 General Module Register
926
15.3.2 Timer/Capture Registers
928
15.3.3 Compare Registers
932
15.3.4 Interrupt Registers
935
16 Watchdog Timer
939
16.1 Watchdog Timer Overview
939
16.2 Features of the Watchdog Timer
940
16.3 The Endinit Function
941
16.4 Watchdog Timer Operation
943
16.4.1 WDT Register Overview
944
16.4.2 Operating Modes of the Watchdog Timer
945
16.4.2.1 Time-Out Mode
946
16.4.2.2 Normal Mode
946
16.4.2.3 Disable Mode
946
16.4.2.4 Prewarning Mode
947
16.4.3 Password Access to WDT_CON0
948
16.4.4 Modify Access to WDT_CON0
949
16.4.5 Term Definitions for WDT_CON0 Accesses
950
16.4.6 Detailed Descriptions of the WDT Modes
951
16.4.6.1 Time-Out Mode Details
951
16.4.6.2 Normal Mode Details
952
16.4.6.3 Disable Mode Details
953
16.4.6.4 Prewarning Mode Details
954
16.4.6.5 WDT Operation During Power-Saving Modes
955
16.4.6.6 WDT Operation in OCDS Suspend Mode
955
16.4.7 Determining WDT Periods
956
16.4.7.1 Time-out Period
956
16.4.7.2 Normal Period
958
16.4.7.3 WDT Period During Power-Saving Modes
959
16.5 Handling the Watchdog Timer
960
16.5.1 System Initialization
960
16.5.2 Re-opening Access to Critical System Registers
961
16.5.3 Servicing the Watchdog Timer
961
16.5.4 Handling the User-Definable Password Field
962
16.5.5 Determining the Required Values for a WDT Access
965
16.6 Watchdog Timer Registers
966
16.6.1 Watchdog Timer Control Register 0
967
16.6.2 Watchdog Timer Control Register 1
969
16.6.3 Watchdog Timer Status Register
970
17 On-Chip Debug Support
973
17.1 Overview
973
17.2 OCDS Level 1
976
17.2.1 TriCore CPU Level 1 OCDS
976
17.2.1.1 Basic Concept
977
17.2.1.2 Debug Event Generation
978
17.2.1.3 Debug Actions
979
17.2.1.4 TriCore OCDS Registers
980
17.2.2 PCP OCDS Level 1
980
17.2.3 BCU OCDS Level 1
981
17.2.4 DMA OCDS Level 1
981
17.3 OCDS Level 2 Debugging via Trace Port
982
17.3.1 TriCore CPU and PCP OCDS Level 2 Trace
982
17.3.2 DMA OCDS Level 2 Trace
982
17.3.3 Concurrent Debugging
983
17.4 Debug Interface (Cerberus)
984
17.4.1 RW Mode
984
17.4.2 Communication Mode
985
17.4.3 Triggered Transfers
985
17.4.4 Multi Core Break Switch
985
17.5 JTAG Interface
987
17.6 Cerberus and JTAG Registers
988
18 Register Overview
990
18.1 Address Map of Segment 15
991
18.2 Registers Tables
996
19 Asynchronous/Synchronous Serial Interface (ASC)
1116
19.1 ASC Kernel Description
1116
19.1.1 Overview
1117
19.1.2 General Operation
1118
19.1.3 Asynchronous Operation
1119
19.1.3.1 Asynchronous Data Frames
1120
19.1.3.2 Asynchronous Transmission
1122
19.1.3.3 Asynchronous Reception
1122
19.1.3.4 RXD/TXD Data Path Selection in Asynchronous Modes
1123
19.1.4 Synchronous Operation
1124
19.1.4.1 Synchronous Transmission
1125
19.1.4.2 Synchronous Reception
1125
19.1.4.3 Synchronous Timing
1126
19.1.5 Baud Rate Generation
1127
19.1.5.1 Baud Rates in Asynchronous Mode
1128
19.1.5.2 Baud Rates in Synchronous Mode
1131
19.1.6 Hardware Error Detection Capabilities
1132
19.1.7 Interrupts
1132
19.2 ASC Kernel Registers
1134
19.2.1 Identification Register
1135
19.2.2 Control Registers
1136
19.2.3 Data Registers
1143
19.3 ASC0/ASC1 Module Implementation
1145
19.3.1 Interfaces of the ASC Modules
1145
19.3.2 ASC0/ASC1 Module Related External Registers
1146
19.3.2.1 ASC0 Clock Control Register
1147
19.3.2.2 Peripheral Input Select Registers
1149
19.3.2.3 Port Control Registers
1151
19.3.2.4 Interrupt Control Registers
1155
19.3.3 DMA Requests
1157
20 Synchronous Serial Interface (SSC)
1158
20.1 SSC Kernel Description
1158
20.1.1 Overview
1159
20.1.2 General Operation
1160
20.1.2.1 Operating Mode Selection
1162
20.1.2.2 Full-Duplex Operation
1163
20.1.2.3 Half-Duplex Operation
1166
20.1.2.4 Continuous Transfers
1167
20.1.2.5 Port Control
1168
20.1.2.6 Transmit FIFO Operation
1169
20.1.2.7 Receive FIFO Operation
1171
20.1.2.8 FIFO Transparent Mode
1173
20.1.2.9 Baud Rate Generation
1175
20.1.2.10 Slave Select Input Operation
1177
20.1.2.11 Slave Select Output Generation Unit
1178
20.1.2.12 Error Detection Mechanisms
1181
20.2 SSC Kernel Registers
1184
20.2.1 Identification Register
1186
20.2.2 Control Registers
1187
20.2.3 Data Registers
1202
20.3 SSC0/SSC1 Module Implementation
1203
20.3.1 Interfaces of the SSC Modules
1203
20.3.2 SSC0/SSC1 Module Related External Registers
1204
20.3.2.1 Clock Control
1205
20.3.2.2 Port Control
1209
20.3.2.3 Interrupt Control Registers
1216
20.3.3 DMA Requests
1217
21 Micro Second Channel (MSC)
1218
21.1 MSC Kernel Description
1220
21.1.1 Overview
1220
21.1.2 Downstream Channel
1222
21.1.2.1 Frame Formats and Definitions
1223
21.1.2.2 Shift Register Operation
1229
21.1.2.3 Transmission Modes
1231
21.1.2.4 Downstream Counter and Enable Signals
1236
21.1.2.5 Baud Rate
1237
21.1.2.6 Abort of Frames
1237
21.1.3 Upstream Channel
1238
21.1.3.1 Data Frames
1239
21.1.3.2 Parity Checking
1239
21.1.3.3 Data Reception
1240
21.1.3.4 Baud Rate
1242
21.1.3.5 Spike Filter
1243
21.1.4 I/O Control
1244
21.1.4.1 Downstream Channel Output Control
1244
21.1.4.2 Upstream Channel
1247
21.1.5 MSC Interrupts
1248
21.1.5.1 Data Frame Interrupt
1249
21.1.5.2 Command Frame Interrupt
1249
21.1.5.3 Time Frame Finished Interrupt
1250
21.1.5.4 Receive Data Interrupt
1251
21.1.5.5 Interrupt Request Compressor
1252
21.2 MSC Kernel Registers
1253
21.2.1 Identification Register
1255
21.2.2 Status and Control Registers
1256
21.2.3 Data Registers
1276
21.3 MSC Module Implementation
1279
21.3.1 Interface Connections of the MSC Modules
1279
21.3.2 MSC0/MSC1 Module-Related External Registers
1281
21.3.3 Clock Control
1282
21.3.3.1 Clock Control Register
1284
21.3.3.2 Fractional Divider Register
1285
21.3.4 Port Control
1287
21.3.4.1 Input/Output Function Selection
1287
21.3.4.2 Pad Driver Mode Registers
1291
21.3.5 On-Chip Connections
1293
21.3.5.1 EMGSTOPMSC Signal (from SCU)
1293
21.3.5.2 ALTINH and ALTINL Connections
1293
21.3.5.3 DMA Controller Service Requests
1294
21.3.6 Interrupt Control Registers
1295
22 Controller Area Network (MultiCAN) Controller
1296
22.1 CAN Basics
1297
22.1.1 Addressing and Bus Arbitration
1297
22.1.2 CAN Frame Formats
1298
22.1.2.1 Data Frames
1298
22.1.2.2 Remote Frames
1300
22.1.2.3 Error Frames
1302
22.1.3 The Nominal Bit Time
1303
22.1.4 Error Detection and Error Handling
1304
22.1.5 Different CAN Implementations
1305
22.1.6 TTCAN Basics
1306
22.1.6.1 Time Reference
1306
22.1.6.2 Basic Cycle
1306
22.1.6.3 Global System Time
1307
22.1.6.4 The System Matrix
1307
22.1.6.5 Generation of the Network Time Unit (NTU)
1308
22.1.6.6 Global Time Generation and Drift Correction
1308
22.2 Overview
1309
22.2.1 MultiCAN Module
1310
22.2.2 Time-Triggered Extension (TTCAN)
1312
22.3 MultiCAN Kernel Functional Description
1313
22.3.1 Module Structure
1313
22.3.2 Clock Control
1315
22.3.3 Port Input Control
1317
22.3.4 Suspend Mode
1317
22.3.5 CAN Node Control
1318
22.3.5.1 Bit Timing Unit
1319
22.3.5.2 Bitstream Processor
1320
22.3.5.3 Error Handling Unit
1321
22.3.5.4 CAN Frame Counter
1322
22.3.5.5 CAN Node Interrupts
1322
22.3.6 Message Object List Structure
1324
22.3.6.1 Basics
1324
22.3.6.2 List of Unallocated Elements
1325
22.3.6.3 Connection to the CAN Nodes
1325
22.3.6.4 List Command Panel
1326
22.3.7 CAN Node Analysis Features
1329
22.3.7.1 Analyze Mode
1329
22.3.7.2 Loop-Back Mode
1329
22.3.7.3 Bit Timing Analysis
1330
22.3.8 Message Acceptance Filtering
1332
22.3.8.1 Receive Acceptance Filtering
1332
22.3.8.2 Transmit Acceptance Filtering
1333
22.3.9 Message Postprocessing
1335
22.3.9.1 Message Object Interrupts
1335
22.3.9.2 Pending Messages
1337
22.3.10 Message Object Data Handling
1339
22.3.10.1 Frame Reception
1339
22.3.10.2 Frame Transmission
1342
22.3.11 Message Object Functionality
1345
22.3.11.1 Standard Message Object
1345
22.3.11.2 Single Data Transfer Mode
1345
22.3.11.3 Single Transmit Trial
1345
22.3.11.4 Message Object FIFO Structure
1346
22.3.11.5 Receive FIFO
1348
22.3.11.6 Transmit FIFO
1349
22.3.11.7 Gateway Mode
1350
22.3.11.8 Foreign Remote Requests
1352
22.4 MultiCAN Kernel Registers
1353
22.4.1 Module Identification Register
1356
22.4.2 Global Module Register
1357
22.4.3 CAN Node Registers
1368
22.4.4 Message Object Registers
1386
22.5 Time-Triggered Extension (TTCAN Controller)
1409
22.5.1 Generation of the Local Time
1409
22.5.2 Automatic TUR Adjust
1410
22.5.3 Cycle Time
1410
22.5.3.1 Local Time and Synchronization Marks
1410
22.5.3.2 Time Marks
1411
22.5.3.3 Watch Trigger
1412
22.5.4 Master Reference Mark (Level 2 only)
1412
22.5.5 Transmit Enable Window
1412
22.5.6 Local Offset and Global Time
1413
22.5.7 Transmit Trigger
1414
22.5.8 Reference Message
1415
22.5.8.1 Differences to Normal CAN Messages
1415
22.5.8.2 Transmit Trigger for a Reference Message
1416
22.6 TTCAN Scheduler
1418
22.6.1 Overview
1418
22.6.2 Scheduler Memory
1419
22.6.2.1 Scheduler Entry Types
1420
22.6.2.2 Scheduler Entry Type Description
1421
22.6.2.3 End of Scheduler Memory Entry
1436
22.6.3 Setup of the Scheduler Entries
1437
22.6.4 Reading the Scheduler Entries
1437
22.6.4.1 Instructions During a Basic Cycle
1437
22.6.4.2 Instructions at the End of a Basic Cycle
1438
22.6.5 Scheduler Instruction Sequence
1440
22.6.5.1 BCC and CSM
1440
22.6.5.2 General Instruction Sequence Rules
1441
22.6.5.3 Scheduler Sequence Example
1442
22.7 TTCAN Operation
1443
22.7.1 Configuration
1443
22.7.2 Configuration Error
1443
22.7.3 Synchronization Phase
1444
22.7.4 Time Masters
1444
22.7.4.1 State of a Time Master
1444
22.7.4.2 Strictly Time-Triggered Behavior
1444
22.7.5 Error Handling
1445
22.7.6 Application Watchdog
1445
22.7.7 MSC Handling
1446
22.7.8 TTCAN Interrupt Control
1447
22.8 TTCAN Registers
1449
22.8.1 TTCAN Timing Registers
1452
22.8.2 TTCAN Control / Status / Configuration Registers
1464
22.8.3 Scheduler Registers
1487
22.9 MultiCAN Module Implementation
1494
22.9.1 Interfaces of the MultiCAN Module
1494
22.9.2 MultiCAN Module External Registers
1495
22.9.3 Module Clock Generation
1496
22.9.3.1 Clock Control Registers
1497
22.9.4 Port and I/O Line Control
1500
22.9.4.1 Input/Output Function Selection in Ports
1500
22.9.4.2 CAN Related Input/Output Control Registers
1501
22.9.4.3 Node Receive Input Selection
1502
22.9.4.4 Pad Output Driver Register
1503
22.9.4.5 External CAN Time Trigger Inputs
1504
22.9.4.6 DMA Request Outputs
1504
22.9.5 Interrupt Control
1505
22.9.5.1 Service Request Control Registers
1507
22.9.6 Parity Protection for CAN Memories
1508
22.9.6.1 CAN Module Register Map
1509
23 Micro Link Interface (MLI)
1510
23.1 Functional Description
1511
23.1.1 General Introduction
1511
23.1.1.1 MLI Overview
1511
23.1.1.2 Naming Conventions
1512
23.1.1.3 MLI Communication Principles
1515
23.1.2 MLI Frame Structure
1519
23.1.2.1 General Frame Layout
1520
23.1.2.2 Copy Base Address Frame
1521
23.1.2.3 Write Offset and Data Frame
1522
23.1.2.4 Optimized Write Frame
1523
23.1.2.5 Discrete Read Frame
1524
23.1.2.6 Optimized Read Frame
1525
23.1.2.7 Command Frame
1526
23.1.2.8 Answer Frame
1527
23.1.3 Handshake Description
1528
23.1.3.1 Handshake Signals
1530
23.1.3.2 Error-free Handshake
1530
23.1.3.3 Ready Delay Time
1531
23.1.3.4 Non-Acknowledge Error
1532
23.1.4 Parity Generation
1533
23.1.5 Address Prediction
1533
23.2 Module Kernel Description
1534
23.2.1 Frame Handling
1534
23.2.1.1 Copy Base Address Frame
1535
23.2.1.2 Write/Data Frames
1537
23.2.1.3 Read Frames
1541
23.2.1.4 Answer Frame
1546
23.2.1.5 Command Frame
1548
23.2.2 General MLI Features
1551
23.2.2.1 Parity Check and Parity Error Indication
1551
23.2.2.2 Non-Acknowledge Error
1554
23.2.2.3 Address Prediction
1554
23.2.2.4 Automatic Data Mode
1555
23.2.2.5 Memory Access Protection
1556
23.2.2.6 Transmit Priority
1557
23.2.2.7 Transmission Delay
1557
23.2.3 Interface Description
1558
23.2.3.1 Transmitter I/O Line Control
1560
23.2.3.2 Receiver I/O Line Control
1560
23.2.3.3 Connecting Several MLI Modules
1562
23.2.4 MLI Service Request Generation
1564
23.2.5 Transmitter Events
1566
23.2.5.1 Parity/Time-out Error Event
1567
23.2.5.2 Normal Frame Sent x Event
1567
23.2.5.3 Command Frame Sent Events
1568
23.2.6 Receiver Events
1569
23.2.6.1 Discarded Read Answer Event
1569
23.2.6.2 Memory Access Protection/Parity Error Event
1570
23.2.6.3 Normal Frame Received/Move Engine Terminated Event
1571
23.2.6.4 Interrupt Command Frame Event
1572
23.2.6.5 Command Frame Received Event
1573
23.2.7 Baud Rate Generation
1574
23.2.8 Automatic Register Overwrite
1575
23.3 Operating the MLI
1576
23.3.1 Connection Setup
1577
23.3.2 Local Transmitter and Pipe Setup
1578
23.3.3 Remote Receiver Setup
1578
23.3.4 Remote Transmitter and Local Receiver Setup
1579
23.3.5 Delay Adjustment
1580
23.3.6 Connection to DMA Mechanism
1582
23.3.7 Connection of MLI to SPI
1582
23.4 MLI Kernel Registers
1584
23.4.1 General Module Registers
1587
23.4.2 General Status/Control Registers
1590
23.4.3 Access Protection Registers
1597
23.4.4 Transmitter Status/Control Registers
1599
23.4.5 Transmitter Data/Address Registers
1610
23.4.6 Transmitter Interrupt Registers
1614
23.4.7 Receiver Status/Control Registers
1619
23.4.8 Receiver Data/Address Registers
1623
23.4.9 Receiver Interrupt Registers
1626
23.5 Implementation of the MLI0/MLI1 in TC1796
1633
23.5.1 Interfaces of the MLI Modules
1633
23.5.2 MLI Module External Registers
1636
23.5.2.1 Automatic Register Overwrite
1636
23.5.3 Module Clock Generation
1637
23.5.4 Port Control and Connections
1639
23.5.4.1 Input/Output Function Selection
1639
23.5.4.2 Input/Output Control Register
1642
23.5.4.3 Pad Driver Characteristics Selection
1646
23.5.5 On-Chip Connections
1648
23.5.5.1 Service Request Output Connections
1648
23.5.5.2 Break Signals
1649
23.5.6 Access Protection
1650
23.5.6.1 Fixed Address Range Definition
1650
23.5.6.2 Programmable Address Sub-Range Definitions
1652
23.5.7 MLI0/MLI1 Transfer Window Address Maps
1655
24 General Purpose Timer Array (GPTA)
1656
24.1 GPTA Overview
1657
24.1.1 Functionality of GPTA0 and GPTA1
1658
24.1.2 Functionality of LTCA2
1660
24.2 GPTA0/GPTA1 Kernel Description
1661
24.2.1 GTPA Units
1662
24.2.2 Clock Generation Unit
1663
24.2.2.1 Filter and Prescaler Cell (FPC)
1665
24.2.2.2 Phase Discrimination Logic (PDL)
1674
24.2.2.3 Duty Cycle Measurement Unit (DCM)
1679
24.2.2.4 Digital Phase Locked Loop Cell (PLL)
1683
24.2.2.5 Clock Distribution Unit (CDU)
1690
24.2.3 Signal Generation Unit
1692
24.2.3.1 Global Timers (GT)
1692
24.2.3.2 Global Timer Cell (GTC)
1710
24.2.3.3 Local Timer Cell (LTC00 to LTC62)
1722
24.2.3.4 Local Timer Cell LTC63
1734
24.2.3.5 LTC Application Examples
1741
24.2.4 Input/Output Line Sharing Unit (IOLS)
1745
24.2.4.1 FPC Input Line Selection
1749
24.2.4.2 GTC and LTC Output Multiplexer Selection
1750
24.2.4.3 GTC Input Multiplexer Selection
1755
24.2.4.4 LTC Input Multiplexer Selection
1760
24.2.4.5 Multiplexer Register Array Programming
1765
24.2.5 Interrupt Sharing Unit (IS)
1767
24.2.6 Pseudo Code Description of GPTA Kernel Functionality
1770
24.2.6.1 FPC Algorithm
1770
24.2.6.2 PDL-Algorithm
1776
24.2.6.3 DCM-Algorithm
1780
24.2.6.4 PLL-Algorithm
1783
24.2.6.5 GT-Algorithm
1785
24.2.6.6 GTC-Algorithm
1786
24.2.6.7 LTC-Algorithm for Cells 0 to 62
1792
24.2.6.8 LTC Algorithm for Cell 63
1799
24.2.7 Programming of a GPTA Module
1803
24.3 GPTA0/1 Kernel Registers
1805
24.3.1 Identification Register
1809
24.3.2 FPC Registers
1810
24.3.3 Phase Discriminator Registers
1814
24.3.4 Duty Cycle Measurement Registers
1816
24.3.5 Digital Phase Locked Loop Registers
1820
24.3.6 Global Timer Registers
1825
24.3.7 Clock Bus Register
1828
24.3.8 Global Timer Cell Registers
1830
24.3.9 Local Timer Cell Registers
1835
24.3.10 I/O Sharing Unit Registers
1846
24.3.11 Multiplexer Control Registers
1849
24.3.12 Service Request Registers
1861
24.4 LTCA2 Kernel Description
1872
24.4.1 Local Timer Cell (LTC00 to LTC62)
1873
24.4.2 Input/Output Line Sharing Unit (IOLS)
1873
24.4.2.1 Output Multiplexer
1876
24.4.2.2 LTC Input Multiplexing Scheme
1880
24.4.2.3 Multiplexer Register Array Programming
1884
24.4.3 Interrupt Sharing Unit (IS)
1886
24.5 LTCA2 Kernel Registers
1888
24.5.1 Bit Protection
1889
24.5.2 Service Request Registers
1889
24.5.3 Local Timer Cell Registers
1889
24.5.4 Module Identification Register
1890
24.5.5 I/O Sharing Unit Registers
1891
24.5.6 Multiplexer Control Registers
1894
24.5.6.1 Output Multiplexer Control Registers
1894
24.5.6.2 LTC Input Multiplexer Control Registers
1898
24.6 GPTA Module Implementation
1902
24.6.1 Interconnections of the GPTA0/GPTA1/LTCA2 Modules
1902
24.6.2 GPTA Module External Registers
1904
24.6.3 Port Control and Connections
1905
24.6.3.1 I/O Group to Port Line Assignment
1905
24.6.3.2 Input/Output Function Selection
1906
24.6.3.3 Pad Driver Characteristics Selection
1908
24.6.3.4 Emergency Control of GPTA Output Ports Lines
1910
24.6.4 On-Chip Connections
1911
24.6.4.1 Clock Bus Connections
1911
24.6.4.2 MSC Controller Connections
1912
24.6.4.3 GPTA Connections with SCU, MultiCAN, FADC, DMA, Ports
1918
24.6.5 Module Clock Generation
1920
24.6.5.1 Clock Control Registers
1922
24.6.6 Limits of Cascading GTCs and LTCs
1927
24.6.7 Interrupt Registers
1928
24.6.8 GPTA Register Address Map
1929
25 Analog-to-Digital Converter (ADC)
1932
25.1 ADC Kernel Description
1932
25.1.1 Analog Input Connections
1935
25.1.2 Conversion Request Sources
1936
25.1.2.1 Parallel Conversion Request Sources
1936
25.1.2.2 Sequential Conversion Request Sources
1937
25.1.2.3 Parallel Conversion Request Source “Timer”
1939
25.1.2.4 Parallel Conversion Request Source “External Event”
1942
25.1.2.5 Parallel Conversion Request Source “Software”
1945
25.1.2.6 Parallel Conversion Request Source “Auto-Scan”
1946
25.1.2.7 Sequential Conversion Request Source “Channel Injection”
1952
25.1.2.8 Sequential Conversion Request Source “Queue”
1956
25.1.3 Conversion Request Arbitration
1960
25.1.3.1 Source Arbitration Level
1961
25.1.3.2 Arbitration Participation Flags
1961
25.1.3.3 Cancel Functionality
1962
25.1.3.4 Clear of Pending Conversion Requests
1962
25.1.3.5 Arbitration and Synchronized Injection
1963
25.1.3.6 Arbitration Lock
1963
25.1.4 Clock Circuit
1964
25.1.4.1 Conversion Principles
1965
25.1.4.2 Conversion Timing Control (CTC and CPS)
1965
25.1.4.3 Sample Timing Control
1966
25.1.4.4 Power-Up Calibration Time
1967
25.1.5 Reference Voltages (VAREF and VAGND)
1968
25.1.6 Error through Overload Conditions
1969
25.1.7 Limit Checking
1970
25.1.8 Expansion of Analog Channels
1972
25.1.8.1 Inverse Current Injection (Overload) Behavior
1973
25.1.8.2 On Resistance of the External Multiplexer
1973
25.1.8.3 Timing of the External Multiplexer
1973
25.1.8.4 Load Capacitance
1973
25.1.9 Service Request Processing
1974
25.1.9.1 Channel Request Source Control
1976
25.1.9.2 Parallel/Serial Request Source Control
1977
25.1.9.3 Service Request Compressor
1978
25.1.9.4 Service Request Flag Control
1979
25.1.10 Synchronization of Two ADC Modules
1980
25.1.10.1 Synchronized Injection Mode
1981
25.1.10.2 Status Information During Synchronized Conversion
1982
25.1.10.3 Master-Slave Functionality for Synchronized Injection
1982
25.1.10.4 Conversion Timing during Synchronized Conversion
1985
25.1.10.5 Service Request Generation in Synchronized Injection
1985
25.1.10.6 Example for Synchronized Injection
1986
25.2 ADC0/ADC1 Kernel Registers
1988
25.2.1 Identification Register
1990
25.2.2 Channel Registers
1991
25.2.3 Timer Registers
1996
25.2.4 Queue Registers
2000
25.2.5 External Trigger Registers
2004
25.2.6 Auto-Scan Registers
2006
25.2.7 Other Control/Status Registers
2009
25.2.8 Channel Inject Register
2021
25.2.9 Software Request Registers
2023
25.2.10 Service Request Registers
2025
25.3 Implementation of ADC0/ADC1
2031
25.3.1 Interface Connections of the ADC Modules
2031
25.3.2 ADC0/ADC1 Module Related External Registers
2033
25.3.3 Clock Control
2034
25.3.3.1 ADC Clock Control Register
2036
25.3.3.2 ADC Fractional Divider Register
2037
25.3.4 Port Control
2039
25.3.4.1 Input/Output Control Register
2040
25.3.4.2 Pad Output Driver Characteristics Selection
2041
25.3.5 Analog Input Line to Analog Input Channel Connections
2042
25.3.6 On-Chip Connections
2044
25.3.6.1 Reference Voltage Selection
2044
25.3.6.2 Request/Gating Input Signal Connections
2045
25.3.6.3 Service Request Output Lines
2050
25.3.6.4 Service Request Control Registers
2051
25.3.6.5 Die Temperature Sensor
2051
26 Fast Analog-to-Digital Converter (FADC)
2052
26.1 FADC Kernel Description
2053
26.1.1 Analog Inputs
2055
26.1.1.1 Analog Input Stage Configurations
2056
26.1.2 Conversion Timing
2059
26.1.3 Channel Triggers
2060
26.1.4 Channel Timer
2062
26.1.5 Control Logic
2063
26.1.5.1 Conversion Control
2063
26.1.5.2 Static Channel Priority
2063
26.1.5.3 Dynamic Priority Assignment
2063
26.1.5.4 Clock Generation
2064
26.1.5.5 Suspend Mode Behavior
2064
26.1.6 Data Reduction Unit
2064
26.1.6.1 Filter Block Structure
2066
26.1.6.2 Filter Block Operation
2067
26.1.6.3 Filter Concatenation
2070
26.1.6.4 Width of Result Registers
2071
26.1.7 Neighbor Channel Trigger
2072
26.1.8 Offset and Gain Calibration
2073
26.1.8.1 Offset Calibration
2074
26.1.8.2 Gain Calibration
2074
26.1.9 Interrupt Generation
2075
26.2 FADC Kernel Registers
2078
26.2.1 Identification Register
2080
26.2.2 Global Registers
2081
26.2.3 Channel Registers
2092
26.2.4 Filter Registers
2099
26.3 Implementation of FADC
2107
26.3.1 Interfaces of the FADC Module
2107
26.3.2 FADC Module Related External Registers
2108
26.3.3 Clock Control
2109
26.3.3.1 Clock Control Registers
2110
26.3.4 Port Control
2112
26.3.5 Interrupt Control
2114
26.3.6 On-Chip Connections
2115
26.3.6.1 Analog Input Lines
2115
26.3.6.2 Trigger/Gating Source Input Connections
2115
26.3.6.3 Service Request Lines
2116
Keyword Index
2117
Register Index
2132
4
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Infineon Technologies TC1796 Specifications
General
Brand
Infineon Technologies
Model
TC1796
Category
Controller
Language
English
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