EasyManua.ls Logo

Infineon Technologies TC1796 - Page 1892

Infineon Technologies TC1796
2150 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-237 V2.0, 2007-07
GPTA, V2.0
FIFOFULL 2rFIFO Full Status
0
B
FIFO not completely written (write access to
MRADIN allowed).
1
B
FIFO completely written (write access to
MRADIN ignored). Must be re-enabled via
WCRES before array can be re-initialized.
FIFOFILLCNT [13:8] r FIFO Fill Count
This bit field shows the current contents of the write
cycle counter.
0 [7:3],
[31:14]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description

Table of Contents