TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-271 V2.0, 2007-07
GPTA, V2.0
The debug clock control register makes it possible to control the module timer clocks
f
GPTA0
, f
GPTA1
, and f
LTCA2
for debug purposes on the basis of a clock counter.
L2EN 10 rw LTCA2 Timer Clock Enable
0
B
LTCA2 timer clock f
LTCA2
is disabled.
1
B
LTCA2 timer clock f
LTCA2
is enabled.
0 [7:4],
[31:11]
r Reserved
Read as 0; should be written with 0.
GPTA0_DBGCTR
GPTA Debug Clock Control Register (004
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG
CEN
0
rw r
1514131211109876543210
CLKCNT
rwh
Field Bits Type Description
CLKCNT [15:0] rwh Debug Clock Count
This bit field determines the number of clock pulses to
be issued when the debug clock feature is enabled
(DBGCEN = 1). CLKCNT counts down to 0000
H
and
stops when the debug clock feature is enabled.
DBGCEN 31 rw Debug Clock Enable
0
B
The debug clock feature is disabled. The module
timer clocks are always enabled.
1
B
The debug clock feature is enabled. If a non-zero
value is written to bit field CLKCNT the related
number of clock pulses is issued at f
GPTA0
, f
GPTA1
,
and f
LTCA2
.
0 [30:16] r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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