TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-89 V2.0, 2007-07
ADC, V2.0
SYMS 28 rh Synchronized Master/Slave Functionality
This bit is set if this ADC module enters the
master/slave mode. It is cleared after the service
request of synchronization mode is generated.
0
B
This synchronized conversion has not been
triggered by both modules.
1
B
This synchronized conversion has been
triggered by both modules at the same time.
0 [7:4],
[23:21],
[31:29]
r Reserved
Read as 0.
Field Bits Type Description
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