Infineon Technologies TC1796 User Manual

TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-88 V2.0, 2007-07
ADC, V2.0
REQSY 24 rh Requestor of Synchronized Conversion
This bit is set during a synchronized conversion in the
case that this ADC module is the master in the
synchronized conversion.
0
B
No synchronized conversion is performed or
this ADC module provides no master
functionality in the synchronized conversion.
1
B
A synchronized conversion is performed and
this ADC module provides master functionality.
PARSY 25 rh Partner in Synchronized Conversion
This bit is set during a synchronized conversion in the
case that this ADC module is the slave in the
synchronized conversion.
0
B
No synchronized conversion is performed or
this ADC module provides no slave
functionality in the synchronized conversion.
1
B
A synchronized conversion is performed and
this ADC module provides slave functionality.
IENREQ 26 rh Interrupt Enable by Requestor
This bit is set in the master ADC module after the
master finished its synchronized conversion.
0
B
The master does not finish the synchronized
conversion, if any was requested.
1
B
The master finished its synchronized
conversion.
IENPAR 27 rh Interrupt Enable by Partner
This bit is set in the master ADC module after the
slave finished its synchronized conversion.In
master/slave mode, bit IENPAR is driven by the
opposite ADC module after the synchronized
conversion is finished.
0
B
The slave does not finish the synchronized
conversion, if any was requested.
1
B
The slave finished its synchronized conversion.
Field Bits Type Description

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English