TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-87 V2.0, 2007-07
ADC, V2.0
AL 12 rh Arbitration Lock
This bit is set, if the timer running in Arbitration Lock
Mode meets the value specified in TCON.ALB. Bit is
cleared on timer underflow.
0
B
Arbitration Lock Mode is inactive.
1
B
Arbitration Lock Mode is active.
CAL 13 rh Power-Up Calibration Status
This bit indicates the status of the power-up
calibration phase.
0
B
Power-up calibration is finished.
1
B
The ADC is in power-up calibration phase.
SMPL 14 rh Sample Phase Status
This bit indicates whether the ADC is in a sample
phase or not.
0
B
The ADC is currently not in the sample phase.
1
B
The ADC currently samples the analog input
voltage (sample phase).
BUSY 15 rh Busy Status
This bit indicates whether the ADC performs a
conversion or not.
0
B
The ADC is currently idle.
1
B
The ADC currently performs a conversion.
QLP [19:16] rh Queue Level Pointer
This bit field points to the empty queue element with
the lowest queue element number. It is incremented
on a queue load operation; it is decremented after a
queue based conversion is started.
QF 20 rh Queue Full Status
This bit is set on a write action to the last empty queue
element. It is cleared if at least one queue element is
empty.
0
B
At least on queue element is empty.
1
B
Queue is full.
Field Bits Type Description
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