TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-31 V2.0, 2007-07
FADC, V2.0
IRQx
(x = 0-3)
16 + x rh Interrupt Request Flag
This bit indicates that a conversion of channel x has
been finished since it has been cleared by software.
Interrupt requests can also be generated while IRQx
is still set. An interrupt can only be generated when
CFGRx.IEN = 1.
0
B
A conversion has not been finished.
1
B
A conversion has been finished.
Bits IRQx can be set/cleared by software via bits
FMR.SIRQx and FMR.RIRQx (see Page 26-32).
IRQFn
(n = 0-1)
20 + n rh Interrupt Request Flag for Filter n
This bit indicates that a filter sequence of filter n has
been finished (new final result is available) since it
has been cleared by software. Interrupt requests can
also be generated while IRQ is still set. An interrupt
can only be generated when FCRn.IEN = 1.
0
B
A filter sequence has not been finished.
1
B
A filter sequence has been finished.
Bits IRQFn can be set/cleared by software via bits
FMR.SIRQFn and FMR.RIRQFn (see Page 26-32).
0 [7:4],
[15:12],
[31:22]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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