TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-32 V2.0, 2007-07
FADC, V2.0
The bits of the Flag Modification Register FMR allow the flags of the conversion request
status register to be set/cleared by software.
FMR
Flag Modification Register (14
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
S
IRQ
F1
S
IRQ
F0
S
IRQ
3
S
IRQ
2
S
IRQ
1
S
IRQ
0
0
R
IRQ
F1
R
IRQ
F0
R
IRQ
3
R
IRQ
2
R
IRQ
1
R
IRQ
0
r wwwwww r wwwwww
1514131211109876543210
0
S
CRF
3
S
CRF
2
S
CRF
1
S
CRF
0
0
R
CRF
3
R
CRF
2
R
CRF
1
R
CRF
0
r wwww r wwww
Field Bits Type Description
RCRFx
(x = 0-3)
xwReset Conversion Request Flag
This bit allows bit CRSR.CRFx to be cleared by
software.
0
B
No operation
1
B
Bit CRSR.CRFx is cleared (also if bit SCRFx is
written simultaneously with 1)
SCRFx
(x = 0-3)
8 + x w Set Conversion Request Flag
This bit allows bit CRSR.CRFx to be set by software.
0
B
No operation
1
B
Bit CRSR.CRFx is set
RIRQx
(x = 0-3)
16 + x w Reset Interrupt Request Flag
This bit allows bit CRSR.IRQx to be cleared by
software.
0
B
No operation
1
B
Bit CRSR.IRQx is cleared
RIRQFn
(n = 0-1)
20 + n w Reset Interrupt Request Flag for Filter n
This bit allows bit CRSR.IRQFn to be cleared by
software.
0
B
No operation
1
B
Bit CRSR.IRQFn is cleared