TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-42 V2.0, 2007-07
FADC, V2.0
GM [7:6] rw Gating Mode
This bit field determines the functionality of the gating
(enable) signal. It determines whether and under
which condition the generation of conversion
requests by trigger signals is possible.
00
B
Conversion requests are disabled and the
Channel Timer is stopped. CRFx never
becomes set (by hardware).
01
B
Conversion requests and the Channel Timer
are always enabled. CRFx becomes set by
hardware with each active trigger signal.
10
B
Conversion requests and the Channel Timer
are enabled only if the gating source input (as
selected by CFGRx.GSEL) is at high level.
11
B
Conversion requests and the Channel Timer
are enabled only if the gating source input (as
selected by CFGRx.GSEL) is at low level.
TM [9:8] rw Trigger Mode
This bit field enables the triggering and determines
the edge of the trigger source input signal that
generates a conversion trigger signal.
00
B
No conversion trigger signals are generated.
Edge detection unit is switched off.
01
B
A conversion request is generated (if gating
enabled) on a rising edge of a trigger source
input (as selected by CFGRx.TSEL).
10
B
A conversion request is generated (if gating
enabled) on a falling edge of a trigger source
input (as selected by CFGRx.TSEL).
11
B
A conversion request is generated (if gating
enabled) on both, rising and falling, edges of a
trigger source input (as selected by
CFGRx.TSEL).
Field Bits Type Description
To Next Page
Loading...