TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-43 V2.0, 2007-07
FADC, V2.0
CTM [11:10] rw Channel Timer Mode
This bit determines the operating mode of channel x
timer.
00
B
Channel x timer is switched off.
01
B
Channel timer is permanently running.
10
B
Channel timer is running only if ECHTIMx = 1.
11
B
Reserved
A Channel Timer trigger event is generated each time
the channel x timer value reaches 00
H
. While the
Channel Timer is not running (CTM = 00
B
or signal
ECHTIMx = 0), the Channel Timer is loaded with 04
H
.
CTF [14:12] rw Channel Timer Frequency
This bit field controls the channel x timer input clock
f
CT
(enable control and frequency selection).
000
B
f
CTx
is disabled.
001
B
f
CTx
is enabled with frequency f
FADC
.
010
B
f
CTx
is enabled with frequency f
FADC
/ 4.
011
B
f
CTx
is enabled with frequency f
FADC
/ 16.
100
B
f
CTx
is enabled with frequency f
FADC
/ 64.
101
B
f
CTx
is enabled with frequency f
FADC
/ 256.
110
B
f
CTx
is enabled with frequency f
FADC
/ 1024.
111
B
Reserved; do not use this combination.
CTREL [23:16] rw Channel Timer Reload Value
This bit field determines the reload value of the
Channel Timer CHTIMx. The divider factor for the
channel x timer is given by:
CTREL + 1, if 2 ≤ f
CLC
/ f
CTx
CTREL + 2, if f
CLC
/ f
CTx
= 1
If CTREL = 0, no trigger event is generated. See also
description on Page 26-11.
INP [29:28] rw Interrupt Node Pointer
This bit field selects which service request output line
will be activated when a conversion of channel x is
finished while CFGRx.IEN is set.
00
B
Service request output SR0 is selected.
01
B
Service request output SR1 is selected.
10
B
Service request output SR2 is selected.
11
B
Service request output SR3 is selected.
Field Bits Type Description
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