TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-9 V2.0, 2007-07
Buses, V2.0
DBCU_LEATT
DBCU LMB Error Attribute Register (20
H
) Reset Value: XXXX XXX0
H
PBCU_LEATT
PBCU LMB Error Attribute Register (20
H
) Reset Value: XXXX XXX0
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPC 0 TAG RD WR SVM 0 UIS ACK
rh r rh rhrhrh r rh rh
1514131211109876543210
LOC 0 FPITAG 0 LEC
rh r rh r rwh
Field Bits Type Description
LEC 0rwhLock Error Capture
This bit indicates and controls whether the error-
capture mechanism is unlocked or locked.
0
B
The error-capture mechanism is unlocked.
The next LMB bus error will be captured.
1
B
The error-capture mechanism is locked. The
registers LEADDR, LEDATL, LEDATH, and
bits [31:4] of LEATT contain valid data.
LEC is automatically set when an LMB bus error has
been captured. Any further LMB bus error is not
captured if LEC = 1. When writing a 1 to LEC, the
error-capture mechanism becomes unlocked and is
ready for the next LMB bus error-capture event.
FPITAG [7:4] rh FPI Bus Master TAG
This bit field indicates the FPI Bus master tag in case
of an LMB bus error.
Note that the FPI Bus master tag is only of interest if
the erroneous LMB transfer was initiated either by
the PCP, DMA, or by Cerberus.
LOC 15 rh LMB Bus Lock State
This bit indicates the bus lock state in case of an
LMB bus error.
0
B
LMB bus error occurred at an atomic transfer.
1
B
LMB bus error occurred at a single or block
transfer.
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