TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-10 V2.0, 2007-07
Buses, V2.0
ACK [18:16] rh LMB Bus Slave Response State
This bit indicates status information of the LMB slave
device in case of an LMB bus error.
000
B
Slave is in normal operation.
010
B
Slave is busy.
011
B
Slave has an error encountered.
other Reserved
UIS 19 rh Un-implemented Address
This bit indicates whether the LMB bus error
occurred by an un-implemented address.
0
B
LMB slave address is valid.
1
B
Invalid LMB slave address occurred.
SVM 21 rh LMB Bus Supervisor Mode
This bit indicates whether the LMB bus error
occurred in supervisor mode or in user mode.
0
B
Transfer was initiated in supervisor mode.
1
B
Transfer was initiated in user modes.
WR 22 rh LMB Bus Write Error Indication
This bit indicates whether the LMB bus error
occurred at a write cycle (see Table 6-5).
RD 23 rh LMB Bus Read Error Indication
This bit indicates whether the LMB bus error
occurred at a read cycle (see Table 6-5).
TAG [26:24] rh LMB Master TAG
This bit field indicates the LMB master device in case
of a LMB bus error.
DBCU_LEATT register (DLMB):
000
B
LFI
001
B
DMI
other Reserved
PBCU_LEATT register (PLMB):
000
B
LMI
001
B
PMI
other Reserved
Field Bits Type Description
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