TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-11 V2.0, 2007-07
Buses, V2.0
LEATT[31:4] contains valid read data only if its bit LEC bit is set.
OPC [31:28] rh LMB Bus Error Transaction Type
This bit field indicates the type of transfer at which
the LMB bus error occurred.
0000
B
8-bit data single transfer
0001
B
16-bit data single transfer
0010
B
32-bit data single transfer
0011
B
64-bit data single transfer
1000
B
2 × 64-bit data block transfer
1001
B
4 × 64-bit data block transfer
other Reserved
0 [3:1],
[14:8],
20, 27
r Reserved
Read as 0; should be written with 0.
Table 6-5 LMB Read/Write Error Indication
RD WR LMB Bus Cycle
0 0 LMB bus error occurred at the read cycle of an atomic transfer.
0 1 LMB bus error occurred at a read cycle of a single transfer.
1 0 LMB bus error occurred at a write cycle of a single transfer or at the
write cycle of an atomic transfer.
1 1 Does not occur
Field Bits Type Description
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