Infineon Technologies TC1796 - Page 342

TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-49 V2.0, 2007-07
Buses, V2.0
SBCU_DBBOS
SBCU Debug Bus Operation Signals Register
(40
H
) Reset Value: 0000 0000
H
RBCU_DBBOS
RBCU Debug Bus Operation Signals Register
(40
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0 RD 0 WR 0 SVM OPC
rrwrrwrrw rw
Field Bits Type Description
OPC [3:0] rw Opcode for Signal Status Debug Trigger
This bit field determines the type (opcode) of a
FPI Bus transaction for which a signal status debug
trigger event is generated (if enabled by
DBCNTL.ONBOS0 = 1).
0000
B
Trigger on single byte transfer selected
0001
B
Trigger on single half-word transfer
selected
0010
B
Trigger on single word transfer selected
0100
B
Trigger on 2-word block transfer selected
0101
B
Trigger on 4-word block transfer selected
0110
B
Trigger on 8-word block transfer selected
1111
B
Trigger on no operation selected
others Reserved
SVM 4rwSVM Signal for Status Debug Trigger
This bit determines the mode of a FPI Bus
transaction for which a signal status debug trigger
event is generated (if enabled by
DBCNTL.ONBOS1 = 1).
0
B
Trigger on user mode selected
1
B
Trigger on supervisor mode selected