TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-51 V2.0, 2007-07
Buses, V2.0
SBCU_DBGNTT
SBCU Debug Trapped Master Register
(44
H
) Reset Value: FFFF FFFF
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH
NR
17
CH
NR
16
CH
NR
15
CH
NR
14
CH
NR
13
CH
NR
12
CH
NR
11
CH
NR
10
CH
NR
07
CH
NR
06
CH
NR
05
CH
NR
04
CH
NR
03
CH
NR
02
CH
NR
01
CH
NR
00
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh
1514131211109876543210
1 CBL
DMA
L
LFI
DMA
H
PCP 1 CBH
r rhrhrhrhrh r rh
Field Bits Type Description
CBH 0rhHigh-Priority Cerberus FPI Bus Master Status
This bit indicates whether the high-priority Cerberus
was SPB bus master when the break trigger event
occurred.
0
B
The high-priority Cerberus was not a SPB bus
master.
1
B
The high-priority Cerberus was SPB bus
master.
PCP 3rhPCP FPI Bus Master Status
This bit indicates whether the PCP was SPB bus
master when the break trigger event occurred.
0
B
The PCP was not a SPB bus master.
1
B
The PCP was SPB bus master at the break
trigger event.
DMAH 4rhHigh-Priority DMA FPI Bus Master Status
This bit indicates whether the high-priority DMA
channels were SPB bus master when the break
trigger event occurred.
0
B
The high-priority DMA channels were not an
SPB bus master.
1
B
The high-priority DMA channels were SPB bus
master. Bits CHNRxy determine the DMA
channel number.
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