Infineon Technologies TC1796 - Page 345

TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-52 V2.0, 2007-07
Buses, V2.0
LFI 5rhLFI Bridge FPI Bus Master Status
This bit indicates whether the LFI Bridge was SPB
bus master when the break trigger event occurred.
0
B
The LFI Bridge was not a SPB bus master.
1
B
The LFI Bridge was SPB bus master.
DMAL 6rhLow-Priority DMA FPI Bus Master Status
This bit indicates whether the low priority DMA
channels were SPB bus master when the break
trigger event occurred.
0
B
The low priority DMA channels were not a SPB
bus master.
1
B
The low priority DMA channels were SPB bus
master. Bits CHNRxy determine the DMA
channel number.
CBL 7rhLow-Priority Cerberus FPI Bus Master Status
This bit indicates whether the low-priority Cerberus
was SPB bus master when the break trigger event
occurred.
0
B
The low-priority Cerberus was not a SPB bus
master.
1
B
The low-priority Cerberus was SPB bus master.
CHNR0y
(y = 0-7)
16 + y rh DMA Channel Number Status
These bits indicate which DMA channel with number
0y was active when a DMA break trigger event
occurred.
0
B
DMA channel 0y was not active at a DMA break
trigger event.
1
B
DMA channel 0y was active at a DMA break
trigger event.
CHNR1y
(y = 0-7)
24+ y rh DMA Channel Number Status
These bits indicate which DMA channel with number
1y was active when a DMA break trigger event
occurred.
0
B
DMA channel 1y was not active at a DMA break
trigger event.
1
B
DMA channel 1y was active at a DMA break
trigger event.
1 [2:1],
[15:8]
r Reserved
Read as 1.
Field Bits Type Description