Infineon Technologies TC1796 - Page 409

TC1796
System Units (Vol. 1 of 2)
Program Memory Unit
User’s Manual 7-58 V2.0, 2007-07
PMU, V2.0
PFDBERM 29 rw PFLASH Double-Bit Error Interrupt Mask
This bit disables/enables the PFLASH double-bit
error interrupt.
0
B
PFLASH double-bit error interrupt is disabled.
1
B
PFLASH double-bit error interrupt is enabled.
DFDBERM 30 rw DFLASH Double-Bit Error Interrupt Mask
This bit disables/enables the DFLASH double-bit
error interrupt.
0
B
DFLASH single-bit error interrupt is disabled.
1
B
DFLASH single-bit error interrupt is enabled.
EOBM 31 rw End-of-Busy Interrupt Mask
This bit enables the end-of-busy interrupt.
0
B
End-of-busy interrupt is disabled.
1
B
End-of-busy interrupt is enabled.
0 7,
[13:12],
[24:22]
r Reserved
Read as 0; should be written with 0.
1) These bits and bit fields can be changed at any time, also with code fetched from Program Flash. A modified
wait state parameter will be taken into account with the next corresponding access.
Field Bits Type Description