TC1796
System Units (Vol. 1 of 2)
Program Memory Unit
User’s Manual 7-57 V2.0, 2007-07
PMU, V2.0
DDFDMA 20 rw Disable Data Fetch from DMA Controller
This bit enables/disables PFLASH and DFLASH data
read accesses that are initiated by the DMA
controller. Once set, this bit can only be cleared when
RPA = 0.
0
B
Data read accesses from PFLASH/DFLASH
initiated by the DMA controller are enabled.
1
B
Data read accesses from PFLASH/DFLASH
initiated by the DMA controller are disabled.
DDFPCP 21 rw Disable Data Fetch from PCP
This bit enables/disables PFLASH and DFLASH data
read accesses that are initiated by the PCP. Once
set, this bit can only be cleared when RPA = 0.
0
B
Data read accesses from PFLASH/DFLASH
initiated by the PCP are enabled.
1
B
Data read accesses from PFLASH/DFLASH
initiated by the PCP are disabled.
SQERM 25 rw Command Sequence Error Interrupt Mask
This bit disables/enables the command sequence
error interrupt.
0
B
Command sequence error interrupt is disabled.
1
B
Command sequence error interrupt is enabled.
PROERM 26 rw Protection Error Interrupt Mask
This bit disables/enables the protection error
interrupt.
0
B
Protection error interrupt is disabled.
1
B
Protection error interrupt is enabled.
PFSBERM 27 rw PFLASH Single-Bit Error Interrupt Mask
This bit disables/enables the PFLASH single-bit error
interrupt.
0
B
PFLASH single-bit error interrupt is disabled.
1
B
PFLASH single-bit error interrupt is enabled.
DFSBERM 28 rw DFLASH Single-Bit Error Interrupt Mask
This bit disables/enables the DFLASH single-bit error
interrupt.
0
B
DFLASH single-bit error interrupt is disabled.
1
B
DFLASH single-bit error interrupt is enabled.
Field Bits Type Description
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