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Infineon Technologies TC1796 - Page 427

Infineon Technologies TC1796
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TC1796
System Units (Vol. 1 of 2)
Data Memory Unit
User’s Manual 8-15 V2.0, 2007-07
DMU, V2.0
OTARx (x = 0-15)
Overlay Target Address Register x
(20
H
+x*C
H
+4
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSEG TBASE
rw rw
1514131211109876543210
TBASE 0
rw r
Field Bits Type Description
TBASE [27:1] rw Target Base
Holds the base address of the overlay memory block in
the target memory. If IEMS is set, bits [9:1] will be
forced to 0 and cannot be modified.
TSEG [31:28] rw Target Segment (reserved)
This bit field is reserved for future use, to select a
segment. In TC1796 implementation, any access to
segments 8
H
, or A
H
will be checked for a valid base
address; return 0 if read; should be written with 0.
0 0rReserved
Read as 0; should be written with 0.

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