TC1796
System Units (Vol. 1 of 2)
Memory Maps
User’s Manual 9-2 V2.0, 2007-07
MemMaps, V2.0
The DLMB address map shows the system addresses from the point of view of the
DLMB master (DMI).
Table 9-1 defines the acronyms and other terms that are used in the address maps
(Table 9-2 to Table 9-5).
Table 9-1 Definition of Acronyms and Terms
Term Description
...BE Means “Bus error” generation
...BET Means “Bus error & trap” generation
RPBBE A bus access is terminated with a bus error on the RPB.
RPBBET A bus access is terminated with a bus error on the RPB and a DSE
trap (read access) or DAE trap (write access).
SPBBE A bus access is terminated with a bus error on the SPB.
SPBBET A bus access is terminated with a bus error on the SPB and a DSE
trap (read access) or DAE trap (write access).
PLMBBE A bus access is terminated with a bus error on the PLMB.
PLMBBET A bus access is terminated with a bus error on the PLMB and a
DSE trap (read access) or DAE trap (write access).
DLMBBE A bus access is terminated with a bus error on the DLMB.
DLMBBET A bus access is terminated with a bus error on the DLMB and a
DSE trap (read access) or DAE trap (write access).
EBUBET If the requested address is configured by the EBU registers and
exist externally, the access is executed. In case of an address
error, a DLMBBET or PLMBBET is generated for a read access.
A PLMBBE is generated for a write access.
EBU access If the requested address is configured by the EBU registers, the
access is executed. In case of an un-configured address, an
“ignore” is applicable for a write access.
For read access, a SPBBE, DLMBBE, and PLMBBE are
generated for PCP2, DMA, and OCDS.
DLMBBE and PLMBBE are generated for DMI.
PLMBBE is generated for PMI.
access A bus access is allowed and is executed.
ignore A bus access is ignored and is not executed. No bus error is
generated.
trap A DSE trap (read access) or DAE trap (write access) is generated.
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